Patents by Inventor John Waranowski

John Waranowski has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Supply voltage disturbance immunity for digital circuits
    Patent number: 10635539
    Abstract: A sensor integrated circuit includes a disturb immune memory configured to store data and a digital processor coupled to the disturb immune memory and including a main register. The digital processor is configured to perform one of a fast reset or slow reset of the main register according to a level of a supply voltage to the integrated circuit. The fast reset includes resetting the main register according to the data stored in the disturb immune memory and the slow reset includes resetting the main register according to a default state.
    Type: Grant
    Filed: May 1, 2018
    Date of Patent: April 28, 2020
    Assignee: Allegro MicroSystems, LLC
    Inventors: Aaron Cook, Kenneth Snowdon, John Waranowski, Virag V. Chaware
  • SUPPLY VOLTAGE DISTURBANCE IMMUNITY FOR DIGITAL CIRCUITS
    Publication number: 20190339985
    Abstract: A sensor integrated circuit includes a disturb immune memory configured to store data and a digital processor coupled to the disturb immune memory and including a main register. The digital processor is configured to perform one of a fast reset or slow reset of the main register according to a level of a supply voltage to the integrated circuit. The fast reset includes resetting the main register according to the data stored in the disturb immune memory and the slow reset includes resetting the main register according to a default state.
    Type: Application
    Filed: May 1, 2018
    Publication date: November 7, 2019
    Applicant: Allegro MicroSystems, LLC
    Inventors: Aaron Cook, Kenneth Snowdon, John Waranowski, Virag V. Chaware