Abstract: Described are memory modules that support different error detection and correction (EDC) schemes in both single- and multiple-module memory systems. The memory modules are width configurable and support the different EDC schemes for relatively wide and narrow module data widths. Data buffers on the modules support the half-width and full-width modes, and also support time-division-multiplexing to access additional memory components on each module in support of enhanced EDC.

Abstract: A memory controller component of a memory system stores memory access requests within a transaction queue until serviced so that, over time, the transaction queue alternates between occupied and empty states. The memory controller transitions the memory system to a low power mode in response to detecting the transaction queue is has remained in the empty state for a predetermined time. In the transition to the low power mode, the memory controller disables oscillation of one or more timing signals required to time data signaling operations within synchronous communication circuits of one or more attached memory devices and also disables one or more power consuming circuits within the synchronous communication circuits of the one or more memory devices.

Abstract: A memory system includes dynamic random-access memory (DRAM) components that include interconnected and redundant component data interfaces. The redundant interfaces facilitate memory interconnect topologies that accommodate considerably more DRAM components per memory channel than do traditional memory systems, and thus offer considerably more memory capacity per channel, without concomitant reductions in signaling speeds. Each DRAM component includes multiplexers that allow either of the data interfaces to write data to or read data from a common set of memory banks, and to selectively relay write and read data to and from other components, bypassing the local banks. Delay elements can impose selected read/write delays to align read and write transactions from and to disparate DRAM components.

Abstract: During system initialization, each data buffer device and/or memory device on a memory module is configured with a unique (at least to the module) device identification number. In order to access a single device (rather than multiple buffers and/or memory devices), a target identification number is written to all of the devices using a command bus connected to all of the data buffer devices or memory devices, respectively. The devices whose respective device identification numbers do not match the target identification number are configured to ignore future command bus transactions (at least until the debug mode is turned off.) The selected device that is configured with a device identification number matching the target identification number is configured to respond to command bus transactions.

Abstract: A memory module comprises an address buffer circuit, a command/address channel, and a plurality of memory components controlled by the address buffer circuit via the command/address channel. At least one memory component comprises a plurality of data ports, a memory core to store data, and a data interface. The data interface is capable of transferring data between the memory core and the data ports. The data interface supports a first data width mode in which the data interface transfers data at a first bit width and a first burst length via the data ports. The data interface also supports a second data width mode in which the data interface transfers data at a second bit width and second burst length via the data ports. The first bit width is greater than the second bit width and the first burst length is shorter than the second burst length.

Abstract: The embodiments described herein describe technologies of dynamic random access memory (DRAM) components for high-performance, high-capacity registered memory modules, such as registered dual in-line memory modules (RDIMMs). One DRAM component may include a set of memory cells and steering logic. The steering logic may include a first data interface and a second data interface. The first and second data interfaces are selectively coupled to a controller component in a first mode and the first data interface is selectively coupled to the controller component in a second mode and the second data interface is selectively coupled to a second DRAM component in the second mode.

Abstract: A combinational logic circuit includes input circuitry to receive a first and second input signals that transition between supply voltages of first and second voltage domain, respectively. The input circuitry generates, based on the first and second input signals, a first internal signal that transitions between one of the supply voltages of the first voltage domain and one of the supply voltages of the second voltage domain. Output circuitry within the combinational logic circuit generates an output signal that transitions between the upper and lower supply voltages of the first voltage domain in response to transition of the first internal signal.

Abstract: A system and method for growing and maintaining biological material including producing a protein associated with the tissue, selecting cells associated with the tissue, expanding the cells, creating at least one tissue bio-ink including the expanded cells, printing the at least one tissue bio-ink in at least one tissue growth medium mixture, growing the tissue from the printed at least one tissue bio-ink, and maintaining viability of the tissue.

Abstract: A system includes a memory controller and a memory device having a command interface, refresh circuitry, control logic, and a plurality of memory banks, each with a plurality of rows of memory cells. The command interface is operable to receive a refresh command from a memory controller and the refresh circuitry is configured to perform one or more refresh operations to refresh data stored in at least one bank of the plurality of memory banks during a refresh time interval in response to the refresh command from the memory controller. The control logic is to configure the command interface to enter a calibration mode during the refresh time interval, and the command interface is configured to perform a calibration operation in the calibration mode during the refresh time interval.

Abstract: A memory module is disclosed. The memory module includes a substrate, and respective first, second and third memory devices. The first memory device is of a first type disposed on the substrate and has addressable storage locations. The second memory device is also of the first type, and includes storage cells dedicated to store failure address information associated with defective storage locations in the first memory device. The third memory device is of the first type and includes storage cells dedicated to substitute as storage locations for the defective storage locations.

Abstract: First data is read out of a core storage array of a memory component over a first time interval constrained by data output bandwidth of the core storage array. After read out from the core storage array, the first data is output from the memory component over a second time interval that is shorter than the first time interval and that corresponds to a data transfer bandwidth greater than the data output bandwidth of the core storage array.

Abstract: A system includes a lidar system, a camera system, and a computing device. The computing device can receive lidar data from the lidar system, receive camera data from the camera system, execute object recognition process(es) to identify, from the camera data, a utility pole and components attached to the utility pole and to create corresponding classified camera data. The computing device can align the camera data with the lidar data and can classify the lidar data to create classified lidar data. The computing device can determine characteristics of the components based on the classified camera data and the classified lidar data. Based on the characteristics, the computing system can perform a pole loading analysis, a clearance analysis, and/or a wire sag analysis.

Abstract: A touch interface device includes a touch surface configured to be engaged by an object, first and second actuator assemblies operably connected to the touch surface, and a controller operably connected with the first and second actuator assemblies. The first actuator assembly displaces the touch surface in one or more lateral directions along the touch surface at a first frequency. The second actuator assembly displaces the touch surface in an angled direction that is one of at least obliquely or perpendicularly angled to the touch surface at a second frequency. The controller operates the first and second actuator assemblies so that the touch surface varies in engagement with the object to impart a force on the object that is along the touch surface.

Abstract: A touch interface device includes a touch surface configured to be engaged by an object, first and second actuator assemblies operably connected to the touch surface, and a controller operably connected with the first and second actuator assemblies. The first actuator assembly displaces the touch surface in one or more lateral directions along the touch surface at a first frequency. The second actuator assembly displaces the touch surface in an angled direction that is one of at least obliquely or perpendicularly angled to the touch surface at a second frequency. The controller operates the first and second actuator assemblies so that the touch surface varies in engagement with the object to impart a force on the object that is along the touch surface.

Abstract: A touch interface device includes a touch surface configured to be engaged by an object, first and second actuator assemblies operably connected to the touch surface, and a controller operably connected with the first and second actuator assemblies. The first actuator assembly displaces the touch surface in one or more lateral directions along the touch surface at a first frequency. The second actuator assembly displaces the touch surface in an angled direction that is one of at least obliquely or perpendicularly angled to the touch surface at a second frequency. The controller operates the first and second actuator assemblies so that the touch surface varies in engagement with the object to impart a force on the object that is along the touch surface.

Abstract: A system and method for identification whereby owners of personal items of value can register against a unique identification number (UID) that is printed, etched or affixed to one or more items. Institutional lost and found offices, such as airline, airport, transit and hotels, and individual finders can use the inventive system to automatically reconcile the lost item by what of its UID and notify the owners or users through an online reporting system. The system and method supplements existing airport luggage tracking systems and more particularly pertains to a new luggage locating system for identification of lost items and a method of automatically identifying the owner of lost items.

Abstract: The present invention relates to a system and method for assessing the impact of an ailment on a health related quality of life domain of a patient using a standardized common metric. The standardized common metric of the present invention enables the impact of various ailments to be compared.

Abstract: The closure device (121) includes interlocking fastening strips (130, 131) and a slider (132) slidably disposed on the fastening strips for facilitating the occlusion and deocclusion of the fastening strips (130, 131) when moved towards first and second ends thereof. A slider (132) is provided for facilitating the attachment of the slider (132) onto the fastening strips (130, 131) in the horizontal X axis (102). The slider (132) provides resistance against the removal of the slider (132) from the fastening strips (130, 131) in the horizontal X axis (102) and the vertical Z axis (106).

Abstract: An electrical cable having a holding member arranged longitudinally along the cable for an optic fiber, which can be used for temperature sensing and/or communications. The holding member can replace one or more strands of the cable, be placed inside an interstice of the cable, be placed in between various layers of the cable, or placed in the jacket of the cable. The cable can be produced through the addition of a planetary strander device to a wire assembly apparatus.