Abstract: A method and apparatus for tracking packets in a processor architecture verification system are disclosed herein. An embodiment of the method comprises identifying a completion event associated with the transfer of a packet across a point to point link network of a virtual bus interface; creating an identification for the packet; and storing data associated with the packet in a database, the data being indexable by way of the identification.

Abstract: A computer implemented method of verifying events generated by an agent includes detecting an input signal at an input of the agent, generating an expected output signal based at least in part on the input signal, detecting an output signal at an output of the agent, wherein the output signal is a translation of the input signal generated by the agent, and comparing the output signal with the expected output signal to verify whether the agent produced the output signal correctly based on the input signal.

Abstract: A computer implemented method of verifying events generated by an agent includes detecting a stimulus at an input of the agent and determining whether generation of an event by the agent in response to the stimulus is conditional. An expectation of the event is created based at least in part on the stimulus, wherein the agent is expected to generate the event. The method also includes making the expectation speculative if the generation of the event is conditional.

Abstract: In one embodiment, a system and method for identifying incomplete transactions includes identifying termination of a test case run on a processor verification system, examining a pending transaction list to identify incomplete transactions, and examining at least one forward progress vector to identify incomplete transactions.

Abstract: Disclosed are systems and methods for identifying erroneous transactions. In one embodiment, a system and a method pertain to monitoring an interface, determining information related to termination of a test case, and after the test case has terminated, identifying an incomplete transaction that should have completed prior to termination of the test case.

Abstract: In one embodiment, a system and method pertain to identifying an output signal having indeterminate timing, creating an expectation for a signal change associated with the output signal, and adding the expectation to an ordered list of expectations for the output signal. In another embodiment, a system and method pertain to detecting a signal change, identifying a vector associated with the signal in which the change occurred, examining pending expectations of the vector until a mature expectation is identified, comparing an expected value contained in the mature expectation with the detected signal change, and reporting an error if the expected value does not match the detected signal change.

Abstract: Systems, methodologies, media, and other embodiments associated with a system for producing a bus-type header-type field from a point-to-point data-type field are described. One exemplary system embodiment includes a logic configured to identify that a point-to-point transaction includes non-memory-data information encoded in a data flit, a logic configured to extract the non-memory-data information from the data flit, and a logic configured to produce a header-type field for a bus-type transaction produced by the virtual bus interface from the point-to-point transaction.

Abstract: A system and method for building a test case operable to test a circuit design, the test case including a summary of instructions. In one embodiment, an instruction generation engine generates a set of instructions of which at least one instruction includes a temporarily uncommitted value. A first summary generation engine portion generates an interfaceable enumeration of the set of instructions wherein each of the temporarily uncommitted values is denoted by an uncommitted reference. A second summary generation engine portion resolves the respective values of the uncommitted references and generates an interfaceable listing of the uncommitted references and their the respective values. The set of instructions and the interfaceable listing of the resolved uncommitted references may be arranged to form the test case.

Abstract: Techniques are disclosed for initializing a representation of a cache in a microprocessor design under test. The cache representation includes a plurality of cache entries, each of which is uniquely referenced by an address-way pair. A test case includes a plurality of cache initialization records, each of which includes a cache entry reference and an initial cache entry value. Each cache entry reference includes an address identifier and a way identifier. An initializer reads the cache initialization records and uses the records which contain valid address-way pairs to initialize cache entries in the cache representation. The initializer then uses the remaining records, in which the way identifier is an invalid (e.g., null) value, to initialize cache entries in the cache representation. Valid way identifiers are selected for these records in a manner which ensures that cache entries are not initialized more than once.

Abstract: Systems, methods and software products are provided for transaction logging and intelligent error reporting in an expectation-based memory agent checker. Simulation status information is appended to one or more transaction log messages generated by the expectation-based memory agent checker. A cause of error indicated by mismatch between simulated output transaction events and expected output transaction events is determined. Information about the error is appended to one or more error messages generated by the expectation-based memory agent checker.

Abstract: Techniques are disclosed for applying input parameters to a parameterized process, such as a computer software program. The input parameters may include both normal parameters and scope-specifying parameters. An input parameter parser initializes and maintains a current scope. The input parameter parser sequentially processes each of the input parameters. If the input parameter is a normal parameter, the parser applies the parameter to the parameterized process. If the input parameter is a scope-specifying parameter, the parser updates the current scope with the scope specified by the scope-specifying parameter. In this way, scope-specifying parameters specify the scope within which subsequent normal parameters are to be applied. The current scope remains in effect until and unless it is modified by one or more scope-specifying parameters. The input parameters may, for example, be implemented in a textual command line which may efficiently specify a variety of parameters having varying scopes.

Abstract: Techniques are disclosed for initializing a representation of a cache in a microprocessor design under test. The cache representation includes a plurality of cache entries, each of which is uniquely referenced by an address-way pair. A test case includes a plurality of cache initialization records, each of which includes a cache entry reference and an initial cache entry value. Each cache entry reference includes an address identifier and a way identifier. An initializer reads the cache initialization records and uses the records which contain valid address-way pairs to initialize cache entries in the cache representation. The initializer then uses the remaining records, in which the way identifier is an invalid (e.g., null) value, to initialize cache entries in the cache representation. Valid way identifiers are selected for these records in a manner which ensures that cache entries are not initialized more than once.

Abstract: A system is disclosed which includes a microprocessor design having a plurality of representations of machine resources of varying scope. The microprocessor design may, for example, have multiple cores and/or be capable of executing multiple threads in hardware. Machine resource representations in the microprocessor design may be limited in scope to a particular thread in a particular core, be shared by multiple threads within a core, or be shared by all threads in all cores. A software routine is provided which allows machine resource representations of varying scopes to be referenced with a fixed number of parameters. When the routine is called with a particular set of parameters, the resource scope referenced by the parameters is determined, and any machine resource representations that are referenced by the parameters are identified. A value may be read from or written to the machine resource representation.