Abstract: A rework re-timer with forward error correction handling is disclosed. An example first intermediate transceiver includes a first interface to communicatively couple the first intermediate transceiver with a first computing device, a second interface to communicatively couple the first intermediate transceiver to a second intermediate transceiver configured to be communicatively coupled with a second computing device, an auto-negotiation controller to: terminate a first auto-negotiation with the first computing device before the first auto-negotiation is completed, transmit, to the second transceiver, first capabilities of the first computing device determined during the first auto-negotiation, and perform a second auto-negotiation with the first computing device utilizing the first capabilities of the first computing device and second capabilities of the second computing device received from the second transceiver.

Abstract: A network re-timer with forward error correction handling is disclosed. An example network re-timer includes a first receiver to receive data from a first connected device and to re-time the data to generate re-timed data, a first transmitter to transmit the re-timed data to a second connected device, a first auto-negotiation handler communicatively coupled to the first receiver to control a first forward error correction mode for communications with the first connected device, and a second auto-negotiation handler communicatively coupled to the first transmitter to control a second forward error correction mode for communications with the second connected device, wherein the first forward error correction mode is different than the second forward error correction mode.

Abstract: A rework re-timer with forward error correction handling is disclosed. An example first intermediate transceiver includes a first interface to communicatively couple the first intermediate transceiver with a first computing device, a second interface to communicatively couple the first intermediate transceiver to a second intermediate transceiver configured to be communicatively coupled with a second computing device, an auto-negotiation controller to: terminate a first auto-negotiation with the first computing device before the first auto-negotiation is completed, transmit, to the second transceiver, first capabilities of the first computing device determined during the first auto-negotiation, and perform a second auto-negotiation with the first computing device utilizing the first capabilities of the first computing device and second capabilities of the second computing device received from the second transceiver.

Abstract: A network re-timer with forward error correction handling is disclosed. An example network re-timer includes a first receiver to receive data from a first connected device and to re-time the data to generate re-timed data, a first transmitter to transmit the re-timed data to a second connected device, a first auto-negotiation handler communicatively coupled to the first receiver to control a first forward error correction mode for communications with the first connected device, and a second auto-negotiation handler communicatively coupled to the first transmitter to control a second forward error correction mode for communications with the second connected device, wherein the first forward error correction mode is different than the second forward error correction mode.

Abstract: Non-inclusive cache systems and methods are provided. In one embodiment a non-inclusive cache system is provided comprising a non-inclusive cache and a cache agent that receives a request for access to the non-inclusive cache and denies the request for access to the non-inclusive cache if the non-inclusive cache system exceeds a predetermined level of activity.

Abstract: Systems and methods are provided to manage access to computing resources. More specifically, certain embodiments are described in which a resource or resource consumer can engage access controls or request that access controls be engaged if the age of a request exceeds one or more thresholds. For example, a requester may, after the age of a request meets or exceeds a threshold, indicate to a destination that a control should be engaged.

Abstract: Systems and methods are provided to manage access to computing resources. More specifically, certain embodiments are described in which a resource or resource consumer can engage access controls or request that access controls be engaged if the age of a request exceeds one or more thresholds. For example, a requester may, after the age of a request meets or exceeds a threshold, indicate to a destination that a control should be engaged.

Abstract: Non-inclusive cache systems and methods are provided. In one embodiment a non-inclusive cache system is provided comprising a non-inclusive cache and a cache agent that receives a request for access to the non-inclusive cache and denies the request for access to the non-inclusive cache if the non-inclusive cache system exceeds a predetermined level of activity.

Abstract: One embodiment is a method of dynamically adjusting a rate at which a dynamic random access memory (“DRAM”) module is refreshed in a computer system. The method comprises monitoring a plurality of system conditions; detecting a change in at least one of the monitored system conditions; responsive to the detection, determining an optimum refresh rate for a current state of the computer system; and setting the refresh rate to the determined optimum refresh rate.

Abstract: A memory subsystem controller and buffer for a computer and a second buffer for memory tag operations. The buffers are linked to the memory controller by two bidirectional data busses. The controller operates the memory subsystem by passing memory addresses to the memory subsystem data bus through the buffers. Unidirectional control interfaces between the controller and the buffers provide memory control commands to both buffers and memory tag information to the tag buffer. The controller performs read and write operations to memory, normally interleaving a plurality of read operations with a plurality of write operations. The read and write data is temporarily stored on the buffer devices while other operations are being executed to optimize the data bandwidth of the memory subsystem of the computer.