Abstract: A computer system including a processor, a system memory, and a boot code storage device. The system memory is connected to the processor and is suitable for storing processor data and instructions. The boot code storage device includes an image selection indicator for indicating which of multiple boot code images are to be loaded. The computer system further includes means for initiating a boot sequence stored on the boot code storage device. The boot sequence selects from first and second boot images based upon the state of the image selection indicator and loads the selected image into the system memory in response to a boot event. In one embodiment, the image selection indicator is in an initial state until the boot code sequence successfully loads a boot image. The image selection indicator is set to a value indicative of the loaded image when one of the boot images is successfully loaded.

Abstract: A computer network that includes a network server and a network client. The network server includes a storage medium configured with boot code data preferably comprising operating system software for the network client. The network client includes a power status indicator and is configured to query the power status indicator as part of a boot code sequence that is initiated in response to a boot event. The network client is configured to schedule retrieval of boot code data from the network server based upon the power status indicator. Preferably, the power status indicator includes a power fail circuit that indicates whether power to the network client has failed since a previous boot event. In one embodiment, the power fail circuit includes a flip flop arranged such that the output of the flip flop is preset when power is restored to the network client after a power failure. Preferably the clear input of the flip flop is programmably assertable.

Abstract: A network computer including a motherboard powered by a power supply via a single power supply plane, a clock generator, a processor, a system memory, and a network interface. The network computer is configured to assume a low power state in response to a low power event and further configured to transition from the low power state to a full power state in response to a wake up event. The wake up event may comprise a LAN wake up in the form of a command issued by a server computer coupled to the network computer via a network. In one embodiment, the network computer lacks a disk based storage device, but includes local permanent storage comprising a compact flash card. Preferably, the network computer's clock generator is configured to produce a clock signal for the processor when the network computer is in the full power mode, and further configured to produce no clock signal in the low power mode.

Abstract: A network computer (12) receives instructions from a network manager (11), including a control interrupt instruction, a system management instruction, and a release instruction. A processor (16) associated with the network computer (12) executes the control interrupt instruction first to produce a control interrupt signal. This control interrupt signal causes an operating status controller (17) associated with the network computer (12) to disable local operational status control at the network computer. After local operational status control is disabled at the network computer (12), the processor (16) executes the system management instruction and performs a system management operation at the network computer. Finally, after the system management operation is completed, the processor (16) executes the release instruction to produce a release signal. The release signal causes the operational status controller (17) to enable local operational status control at the network computer (12).

Abstract: A system reset arrangement (12) resides alternately in an enabled condition or a disabled condition. When the system reset arrangement (12) is in the disabled condition, a switching input provided through a switch (11) does not effect a system reset. However, in the enabled condition, the switching input through the switch (11) causes system reset arrangement (12) to produce a reset output which resets the system. A reset disable arrangement (14) maintains the system reset arrangement (12) in the disabled condition in response to a disable input. When the disable input is removed, reset disable arrangement (14) maintains system reset arrangement (12) in the enabled condition. An interrupt output (15) develops an interrupt signal in response to the switching input. This interrupt signal prompts an interrupt controller (16) to issue a desired system management command to be processed by the system processor.