Abstract: Analog to digital converters with enhanced performance in the presence of clock noise interference are configured with sampling clock phase selection circuitry to enable operation of the converter at the optimum sampling time intervals with respect to the interfering noise. The selection circuitry includes apparatus for generating a plurality of sampling clock phases and a multiplexer coupled to the plurality of phases to select the optimum clock phase.

Abstract: A video clock input signal is applied to a delay line comprising a cascade connection of a plurality of delay elements formed in an integrated circuit for providing a plurality of delayed clock signals at respective taps of the delay line. A selection circuit, responsive to a horizontal synchronizing signal supplied thereto, couples a selected one of the taps to an output for providing a delayed output clock signal that is edge-aligned with the synchronizing signal. For reducing the number of taps required to provide a given minimum delay step resolution and a given minimum total delay for delay elements which may vary in delay, from one integrated circuit to another, the taps are spaced one element apart for a first group of the delay elements and are spaced more than one element apart for at least one second group of the elements.