Patents by Inventor John William Marshall

John William Marshall has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7447872
    Abstract: An inter-chip communication (ICC) mechanism enables any processor in a pipelined arrayed processing engine to communicate directly with any other processor of the engine over a low-latency communication path. The ICC mechanism includes a unidirectional control plane path that is separate from a data plane path of the engine and that accommodates control information flow among the processors. The mechanism thus enables inter-processor communication without sending messages over the data plane communication path extending through processors of each pipeline.
    Type: Grant
    Filed: May 30, 2002
    Date of Patent: November 4, 2008
    Assignee: Cisco Technology, Inc.
    Inventors: Russell Schroter, John William Marshall, Kenneth H. Potter
  • Patent number: 7185224
    Abstract: A processor isolation technique enhances debug capability in a multiprocessor circuit. A bypass register has a bit location which may indicate that a processor is to be bypassed. A code entry point is selected to permit a downstream processor to do the work of the bypassed processor. The processors may be arrayed in a pipeline.
    Type: Grant
    Filed: December 10, 2003
    Date of Patent: February 27, 2007
    Assignee: Cisco Technology, Inc.
    Inventors: William Fredenburg, Kenneth Michael Key, Michael L. Wright, John William Marshall
  • Patent number: 7139899
    Abstract: An instruction decode mechanism enables an instruction to control data flow bypassing hardware within a pipelined processor of a programmable processing engine. The control mechanism is defined by an instruction set of the processor as a unique register decode value that specifies either source operand bypassing (via a source bypass operand) or result bypassing (via a result bypass operand) from a previous instruction executing in pipeline stages of the processor. The source bypass operand allows source operand data to be shared among the parallel execution units of the pipelined processor, whereas the result bypass operand explicitly controls data flow within a pipeline of the processor through the use of result bypassing hardware of the processor. The instruction decode control mechanism essentially allows an instruction to directly identify a pipeline stage register for use as its source operand.
    Type: Grant
    Filed: September 3, 1999
    Date of Patent: November 21, 2006
    Assignee: Cisco Technology, Inc.
    Inventors: Darren Kerr, John William Marshall
  • Patent number: 7100021
    Abstract: A mechanism synchronizes among processors of a processing engine in an intermediate network station. The processing engine is configured as a systolic array having a plurality of processors arrayed as rows and columns. The mechanism comprises a barrier synchronization mechanism that enables synchronization among processors of a column (i.e., different rows) of the systolic array. That is, the barrier synchronization function allows all participating processors within a column to reach a common point within their instruction code sequences before any of the processors proceed.
    Type: Grant
    Filed: October 16, 2001
    Date of Patent: August 29, 2006
    Assignee: Cisco Technology, Inc.
    Inventors: John William Marshall, Barry S. Burns, Darren Kerr
  • Patent number: 6986022
    Abstract: A mechanism synchronizes instruction code executing on a processor of a processing engine in an intermediate network station. The processing engine is configured as a systolic array having a plurality of processors arrayed as rows and columns. The mechanism comprises a boundary (temporal) synchronization mechanism for cycle-based synchronization within a processor of the array. The synchronization mechanism is generally implemented using specialized synchronization micro operation codes (“opcodes”).
    Type: Grant
    Filed: October 16, 2001
    Date of Patent: January 10, 2006
    Assignee: Cisco Technology, Inc.
    Inventors: John William Marshall, Barry S. Burns, Darren Kerr
  • Patent number: 6973521
    Abstract: A lock controller supports both blocking and non-blocking lock requests issued by processors of a processing engine when attempting to access a shared resource of an intermediate network device. The non-blocking lock controller capability provides a processor with the flexibility to obtain other shared resources if the originally requested resource is not available. The blocking capability of the lock controller guarantees that each processor will eventually obtain the requested resource. By supporting both blocking and non-blocking capabilities, the lock controller provides increased flexibility and performance to the processors of the processing engine.
    Type: Grant
    Filed: May 16, 2000
    Date of Patent: December 6, 2005
    Assignee: Cisco Technology, Inc.
    Inventors: Atri Indiresan, Felix Yuan, Iwan Kartawira, John William Marshall, Russell Schroter
  • Patent number: 6965615
    Abstract: A technique is provided for striping packets across pipelines of a processing engine within a network switch. The processing engine comprises a plurality of processors arrayed as pipeline rows and columns embedded between input and output buffers of the engine. Each pipeline row or cluster includes a context memory having a plurality of window buffers of a defined size. Each packet is apportioned into fixed-sized contexts corresponding to the defined window size associated with each buffer of the context memory. The technique includes a mapping mechanism for correlating each context with a relative position within the packet, i.e., the beginning, middle and end contexts of a packet. The mapping mechanism facilitates reassembly of the packet at the output buffer, while obviating any any out-of-order issues involving the particular contexts of a packet.
    Type: Grant
    Filed: September 18, 2000
    Date of Patent: November 15, 2005
    Assignee: Cisco Technology, Inc.
    Inventors: Darren Kerr, Jeffery Scott, John William Marshall, Scott Nellenbach
  • Patent number: 6920562
    Abstract: An encryption mechanism tightly-couples hardware data encryption functions with software-based protocol decode processing within a pipelined processor of a programmable processing engine. Tight-coupling is achieved by a micro-architecture of the pipelined processor that allows encryption functions to be accessed as a novel encryption execution unit of the processor. Such coupling substantially reduces the latency associated with conventional hardware/software interfaces.
    Type: Grant
    Filed: December 18, 1998
    Date of Patent: July 19, 2005
    Assignee: Cisco Technology, Inc.
    Inventors: Darren Kerr, John William Marshall
  • Patent number: 6804815
    Abstract: A sequence control mechanism enables out-of-order processing of contexts by processors of a symmetric multiprocessor system having a plurality of processors arrayed as a processing engine. The processors of the engine are preferably arrayed as a plurality of rows or clusters embedded between input and output buffers, wherein each cluster of processors is configured to process contexts in a first in, first out (FIFO) synchronization order. However, the sequence control mechanism allows out-of-order context processing among the clusters of processors, while selectively enforcing FIFO synchronization ordering among those clusters on an as needed basis, i.e., for certain contexts. As a result, the control mechanism reduces undesired processing delays among those processors.
    Type: Grant
    Filed: September 18, 2000
    Date of Patent: October 12, 2004
    Assignee: Cisco Technology, Inc.
    Inventors: Darren Kerr, Jeffery B. Scott, John William Marshall, Kenneth H. Potter, Scott Nellenbach
  • Patent number: 6728839
    Abstract: An enhanced prefetching technique enables control of internal activities of a cache memory by a processor without relying on conventional algorithms. The cache memory is contained within a processor complex of a programmable arrayed processing engine used to efficiently process data within an intermediate network station of a computer network. The cache may further assume various functions while providing an interface to an external memory of the station via a memory controller. That is, the cache may function as a read buffer, a write buffer and/or a buffer for pending atomic commands, each of which is merged into a single memory bank that can be partitioned in any manner to enable efficient utilization.
    Type: Grant
    Filed: October 28, 1998
    Date of Patent: April 27, 2004
    Assignee: Cisco Technology, Inc.
    Inventor: John William Marshall
  • Patent number: 6681341
    Abstract: A processor isolation technique enhances debug capability in a highly integrated multiprocessor circuit containing a programmable arrayed processing engine for efficiently processing transient data within an intermediate network station of a computer network. The technique comprises a mechanism for programming a code entry point for each processor of a processor complex utilizing a register set that is accessible via an out-of-band bus coupled to a remote processor of the engine. The programmable entry point mechanism operates in conjunction with a bypass capability that passes transient data through a processor complex that is not functional, not running or otherwise unable to process data. Another aspect of the debug technique involves the ability to override completion control signals provided by each processor complex in order to advance a pipeline of the processing engine.
    Type: Grant
    Filed: November 3, 1999
    Date of Patent: January 20, 2004
    Assignee: Cisco Technology, Inc.
    Inventors: William Fredenburg, Kenneth Michael Key, Michael L. Wright, John William Marshall
  • Patent number: 6662252
    Abstract: A group and virtual locking mechanism (GVLM) addresses two classes of synchronization present in a system having resources that are shared by a plurality of threads of execution: (1) synchronization of the multi-access shared resources; and (2) simultaneous requests for the shared resources. Broadly stated, the novel GVLM comprises a lock controller function associated with each thread of execution, and lock instructions executed by the threads that manipulate the lock controller to create a tightly integrated arrangement for issuing lock requests to the shared resources. The plurality of threads of execution may each execute in a different processor. Alternatively, the plurality of threads of execution may each execute in a single processor.
    Type: Grant
    Filed: December 8, 2002
    Date of Patent: December 9, 2003
    Assignee: Cisco Technology, Inc.
    Inventors: John William Marshall, Kenneth H. Potter
  • Publication number: 20030225995
    Abstract: An inter-chip communication (ICC) mechanism enables any processor in a pipelined arrayed processing engine to communicate directly with any other processor of the engine over a low-latency communication path. The ICC mechanism includes a unidirectional control plane path that is separate from a data plane path of the engine and that accommodates control information flow among the processors. The mechanism thus enables inter-processor communication without sending messages over the data plane communication path extending through processors of each pipeline.
    Type: Application
    Filed: May 30, 2002
    Publication date: December 4, 2003
    Inventors: Russell Schroter, John William Marshall, Kenneth H. Potter
  • Publication number: 20030159021
    Abstract: An instruction decode mechanism enables an instruction to control data flow bypassing hardware within a pipelined processor of a programmable processing engine. The control mechanism is defined by an instruction set of the processor as a unique register decode value that specifies either source operand bypassing (via a source bypass operand) or result bypassing (via a result bypass operand) from a previous instruction executing in pipeline stages of the processor. The source bypass operand allows source operand data to be shared among the parallel execution units of the pipelined processor, whereas the result bypass operand explicitly controls data flow within a pipeline of the processor through the use of result bypassing hardware of the processor. The instruction decode control mechanism essentially allows an instruction to directly identify a pipeline stage register for use as its source operand.
    Type: Application
    Filed: September 3, 1999
    Publication date: August 21, 2003
    Inventors: DARREN KERR, JOHN WILLIAM MARSHALL
  • Patent number: 6529983
    Abstract: A group and virtual locking mechanism (GVLM) addresses two classes of synchronization present in a system having resources that are shared by a plurality of processors: (1) synchronization of the multi-access shared resources; and (2) simultaneous requests for the shared resources. The system is a programmable processing engine comprising an array of processor complex elements, each having a microcontroller processor. The processor complexes are preferably arrayed as rows and columns. Broadly stated, the novel GVLM comprises a lock controller function associated with each column of processor complexes and lock instructions executed by the processors that manipulate the lock controller to create a tightly integrated arrangement for issuing lock requests to the shared resources.
    Type: Grant
    Filed: November 3, 1999
    Date of Patent: March 4, 2003
    Assignee: Cisco Technology, Inc.
    Inventors: John William Marshall, Kenneth H. Potter
  • Patent number: 6208661
    Abstract: The present invention provide for scheduling protocol data units for transmission on a virtual channel. The scheduling is accomplished by first determining a relative theoretical departure time for a protocol data unit. Departure times are identified in each of a plurality of time domains based upon the relative theoretical departure time for the protocol data unit. An identified departure times is selected from a time domain and the protocol data unit is scheduled for transmission during the selected available departure time.
    Type: Grant
    Filed: January 7, 1998
    Date of Patent: March 27, 2001
    Assignee: International Business Machines Corporation
    Inventor: John William Marshall
  • Patent number: 3958220
    Abstract: Multiple symbol correction employing auxiliary pointers is enhanced by unique interaction of code structures either with ambiguous auxiliary pointers or data structures for precisely locating errors. For example, a code apparatus can correct two symbols in error only with two error location pointers; with three error location pointers, the code cannot correct the errors since error location is ambiguous. Once this has been determined, the features set forth in the present invention are employed to delimit the error burst such that the code apparatus may correct two symbols in error, even with ambiguous error location pointers. With no auxiliary pointers, methods and apparatus can create such auxiliary pointers in particular data structures and error patterns.
    Type: Grant
    Filed: May 30, 1975
    Date of Patent: May 18, 1976
    Assignee: International Business Machines Corporation
    Inventor: John William Marshall