Abstract: Apparatus and methods related to multipath bandpass filters with passband notches are provided herein. In certain configurations, a multipath bandpass filter includes multiple filter circuit branches or paths that are electrically connected in parallel with one another between an input terminal and an output terminal. The input terminal receives an input signal, and each filter circuit branch includes a downconverter that downconverts the input signal to generate a downconverted signal, a filter network that generates a filtered signal by filtering the downconverted signal, and an upconverter that upconverts the filtered signal to generate a branch output signal. The filter network includes at least one low pass filter and at least one notch filter to provide a passband with in-band notches. The branch output signals from the filter circuit branches are combined to generate an output signal at the output terminal.

Abstract: A variable capacitor is disclosed, having a variable capacitance between a first node and a second node. The variable capacitor comprises a switch having a first terminal and a second terminal, the impedance between the first terminal and the second terminal being controllable via a control node. The variable capacitor further includes a first capacitor coupled between the first terminal and the first node, and a second capacitor coupled between the second terminal and the second node.

Abstract: Apparatus and methods for oscillation suppression of cascode power amplifiers are provided herein. In certain implementations, a power amplifier system includes a cascode power amplifier including a plurality of transconductance devices that operate in combination with a plurality of cascode devices to amplify a radio frequency input signal. The power amplifier system further includes a bias circuit that biases the plurality of cascode devices with two or more bias voltages that are decoupled from one another at radio frequency to thereby inhibit the cascode power amplifier from oscillating.

Abstract: Multipath filters are provided herein. In certain configurations, a multipath filter includes multiple filter paths or circuit branches that are electrically connected in parallel with one another between an input terminal and an output terminal. The input terminal receives an input signal, and each filter circuit branch includes a double-in double-switched (DIDS) downconverter that downconverts the input signal with two different clock signal phases to generate a downconverted signal. Each filter circuit branch further includes a filter network that generates a filtered signal by filtering the downconverted signal and an upconverter that upconverts the filtered signal to generate a branch output signal. Additionally, the branch output signals from the filter circuit branches are combined to generate an output signal at the output terminal.

Abstract: A power amplifier circuit includes a transistor having a first terminal that is configured to receive an input signal, a second terminal electrically coupled to ground, and a third terminal configured to transmit a combined amplified signal. The power amplifier circuit further includes a combining signal input path electrically coupled to the second terminal and configured to receive a combining signal and provide the combining signal to the second terminal of the transistor to generate, at least in part, the combined amplified signal.

Abstract: A radio-frequency device comprises a first radio-frequency signal node, a second radio-frequency signal node, a first power cell path coupled between the first radio-frequency signal node and a ground reference node, the first power cell path including a first transistor having an input terminal coupled to the second radio-frequency signal node, and a second power cell path coupled in parallel with the first power cell path between the first radio-frequency signal node and the ground reference node, the second power cell path including a second transistor having an input terminal coupled to the second radio-frequency signal node and an output terminal that is electrically isolated from an output terminal of the first transistor.

Abstract: A cascode power cell for a power amplifier circuit includes a radio frequency signal input node, a radio frequency signal output node, and a plurality of sub-cells each including a first transistor having a collector coupled to the radio frequency signal output node, each of the plurality of sub-cells further including a second transistor having a collector coupled to an emitter of the first transistor at a connection node, and a base coupled to the radio frequency signal input node, the connection nodes for each of the plurality of sub-cells being electrically isolated from one another.

Abstract: A power amplifier module includes a driver transistor having first, second, and third terminals, a radio-frequency input port coupled to the first terminal of the driver transistor, a cascode transistor having first, second, and third terminals, the second terminal of the cascode transistor being coupled to the third terminal of the driver transistor, a radio-frequency output port coupled to the second terminal of the cascode transistor, and a coupling path connecting the first terminal of the cascode transistor to the third terminal of the cascode transistor, the coupling path including a capacitor.

Abstract: Circuits, devices and methods are disclosed, including radio-frequency circuitry comprising a polar modulator configured to invert a sampled transmitted signal into an inverted sampled transmitted signal, a signal combiner configured to combine the inverted sampled transmitted signal with a received signal and a control logic circuit coupled to the polar modulator, the control logic circuit configured to adjust one or more tuning parameters of the polar modulator for inverting the sampled transmitted signal.

Abstract: A power amplifier circuit includes a transistor having a first terminal that is configured to receive an input signal, a second terminal electrically coupled to ground, and a third terminal configured to transmit a combined amplified signal. The power amplifier circuit further includes a combining signal input path electrically coupled to the second terminal and configured to receive a combining signal and provide the combining signal to the second terminal of the transistor to generate, at least in part, the combined amplified signal.

Abstract: A radio-frequency module comprises a low-noise amplifier including a common source transistor having a gate node that receives a radio-frequency input signal and a drain node that transmits a combined radio-frequency output signal, and a correction signal input path configured to receive a correction signal and provide the correction signal to a source node of the common source transistor to generate, at least in part, the combined radio-frequency output signal.

Abstract: A variable capacitor is disclosed, having a variable capacitance between a first node and a second node. The variable capacitor comprises a switch having a first terminal and a second terminal, the impedance between the first terminal and the second terminal being controllable via a control node. The variable capacitor further includes a first capacitor coupled between the first terminal and the first node, and a second capacitor coupled between the second terminal and the second node.

Abstract: Apparatus and methods for oscillation suppression of cascode power amplifiers are provided herein. In certain implementations, a power amplifier system includes a cascode power amplifier including a plurality of transconductance devices that operate in combination with a plurality of cascode devices to amplify a radio frequency input signal. The power amplifier system further includes a bias circuit that biases the plurality of cascode devices with two or more bias voltages that are decoupled from one another at radio frequency to thereby inhibit the cascode power amplifier from oscillating.

Abstract: Multipath filters are provided herein. In certain configurations, a multipath filter includes multiple filter paths or circuit branches that are electrically connected in parallel with one another between an input terminal and an output terminal. The input terminal receives an input signal, and each filter circuit branch includes a double-in double-switched (DIDS) downconverter that downconverts the input signal with two different clock signal phases to generate a downconverted signal. Each filter circuit branch further includes a filter network that generates a filtered signal by filtering the downconverted signal and an upconverter that upconverts the filtered signal to generate a branch output signal. Additionally, the branch output signals from the filter circuit branches are combined to generate an output signal at the output terminal.

Abstract: Apparatus and methods related to multipath bandpass filters with passband notches are provided herein. In certain configurations, a multipath bandpass filter includes multiple filter circuit branches or paths that are electrically connected in parallel with one another between an input terminal and an output terminal. The input terminal receives an input signal, and each filter circuit branch includes a downconverter that downconverts the input signal to generate a downconverted signal, a filter network that generates a filtered signal by filtering the downconverted signal, and an upconverter that upconverts the filtered signal to generate a branch output signal. The filter network includes at least one low pass filter and at least one notch filter to provide a passband with in-band notches. The branch output signals from the filter circuit branches are combined to generate an output signal at the output terminal.

Abstract: A power amplifier module includes a driver transistor having first, second, and third terminals, a radio-frequency input port coupled to the first terminal of the driver transistor, a cascode transistor having first, second, and third terminals, the second terminal of the cascode transistor being coupled to the third terminal of the driver transistor, a radio-frequency output port coupled to the second terminal of the cascode transistor, and a coupling path connecting the first terminal of the cascode transistor to the third terminal of the cascode transistor, the coupling path including a capacitor.

Abstract: A time-to-digital converter (TDC) measures a time interval ?TTot between a leading signal and a triggering signal. A phase regulator incorporates a looped delay line to create pre-defined sub-intervals TNOR determined by the length of the delay line. The phase regulator has an input receiving the leading signal such that the leading signal loops around the delay line. A counter for counting the number of times m the leading signal loops around the delay line before said triggering signal arrives to obtain a coarse measurement of the time interval defined in terms of the sub-intervals TNOR. A Vernier core for measures a residual time interval TR where TR=?TTot?mTNOR to obtain a value for the time interval ?TTot. The TDC uses simpler encoding logic with reduced power consumption and phase noise performance better than 5 dB.

Abstract: A radio-frequency (RF) module includes a driver transistor having a base, collector and emitter, an RF input port coupled to the base of the driver transistor, a cascode transistor having a base, collector and emitter, the emitter of the cascode transistor being coupled to the collector of the driver transistor, an RF output port coupled to the collector of the cascode transistor, and a coupling path connecting the base of the cascode transistor to the emitter of the cascode transistor, the coupling path including a capacitor.

Abstract: A time-to-digital converter (TDC) measures a time interval ?TTot between a leading signal and a triggering signal. A phase regulator incorporates a looped delay line to create pre-defined sub-intervals TNOR determined by the length of the delay line. The phase regulator has an input receiving the leading signal such that the leading signal loops around the delay line. A counter for counting the number of times m the leading signal loops around the delay line before said triggering signal arrives to obtain a coarse measurement of the time interval defined in terms of the sub-intervals TNOR. A Vernier core for measures a residual time interval TR where TR=?TTot?mTNOR to obtain a value for the time interval ?TTot. The TDC uses simpler encoding logic with reduced power consumption and phase noise performance better than 5 dB.

Abstract: A cascode power cell for a power amplifier circuit includes a radio frequency signal input node, a radio frequency signal output node, and a plurality of sub-cells each including a first transistor having a collector coupled to the radio frequency signal output node, each of the plurality of sub-cells further including a second transistor having a collector coupled to an emitter of the first transistor at a connection node, and a base coupled to the radio frequency signal input node, the connection nodes for each of the plurality of sub-cells being electrically isolated from one another.