Abstract: A time-to-digital converter (TDC) measures a time interval ?TTot between a leading signal and a triggering signal. A phase regulator incorporates a looped delay line to create pre-defined sub-intervals TNOR determined by the length of the delay line. The phase regulator has an input receiving the leading signal such that the leading signal loops around the delay line. A counter for counting the number of times m the leading signal loops around the delay line before said triggering signal arrives to obtain a coarse measurement of the time interval defined in terms of the sub-intervals TNOR. A Vernier core for measures a residual time interval TR where TR=?TTot?mTNOR to obtain a value for the time interval ?TTot. The TDC uses simpler encoding logic with reduced power consumption and phase noise performance better than 5 dB.

Abstract: A cascode power cell for a power amplifier circuit includes a radio frequency signal input node, a radio frequency signal output node, and a plurality of sub-cells each including a first transistor having a collector coupled to the radio frequency signal output node, each of the plurality of sub-cells further including a second transistor having a collector coupled to an emitter of the first transistor at a connection node, and a base coupled to the radio frequency signal input node, the connection nodes for each of the plurality of sub-cells being electrically isolated from one another.

Abstract: Circuits, devices and methods are disclosed, including a phase shifter configured to provide a bypass state, a single first-handed quarter-wave state, a double first-handed quarter-wave state, or a single second-handed quarter-wave state utilizing two or less inductors. In some implementations, a phase shifter is disclosed to provide a first node and a second node, a first switchable path having a first inductance and a second inductance arranged in series between the first and second nodes, a capacitive grounding path implemented on each side of each of the first and second inductances, at least one of the capacitive grounding paths configured as a switchable capacitive grounding path, and a reconfiguring circuit assembly configured to allow the phase shifter to provide a plurality of quadrant phase shifts utilizing the first and second inductances and the at least one switchable capacitive grounding path.

Abstract: The present invention provides compounds produced by the reaction of glycidyl ethers and glycidyl esters with ether compounds including N,N,N?-trimethyl-bis-(aminoethyl)ether. N,N,N?-trimethyl-bis-(aminoethyl)ether and its derivatives can be used as polyurethane catalysts.

Abstract: Disclosed are circuits and method for reducing or eliminating reference spurs in frequency synthesizers. In some implementations, a phase-locked loop (PLL) such as a Frac-N PLL of a frequency synthesizer can include a phase frequency detector (PFD) configured to receive a reference signal and a feedback signal. The PFD can be configured to generate a first signal representative of a phase difference between the reference signal and the feedback signal. The PLL can further include a compensation circuit configured to generate a compensation signal based on the first signal. The PLL can further includes a voltage-controlled oscillator (VCO) configured to generate an output signal based on the compensation signal. The compensation signal can include at least one feature for substantially eliminating one or more reference spurs associated with the PLL.

Abstract: Circuits, devices and methods are disclosed, including radio-frequency circuitry comprising a polar modulator configured to invert a sampled transmitted signal into an inverted sampled transmitted signal, a signal combiner configured to combine the inverted sampled transmitted signal with a received signal and a control logic circuit coupled to the polar modulator, the control logic circuit configured to adjust one or more tuning parameters of the polar modulator for inverting the sampled transmitted signal.

Abstract: A variable capacitor is disclosed, having a variable capacitance between a first node and a second node. The variable capacitor comprises a switch having a first terminal and a second terminal, the impedance between the first terminal and the second terminal being controllable via a control node. The variable capacitor further includes a first capacitor coupled between the first terminal and the first node, and a second capacitor coupled between the second terminal and the second node.

Abstract: A radio-frequency (RF) module includes a first transistor having a base, a collector, and an emitter, a radio-frequency output transmit path coupled to the collector of the first transistor at a first end and to a radio-frequency output port at a second end, and an output matching network disposed in the radio-frequency output transmit path, the output matching network including a shunt arm coupled to ground, the shunt arm including a switch that is controllable to modify an impedance of the output matching network.

Abstract: A radio-frequency (RF) module includes a driver transistor having a base, collector and emitter, an RF input port coupled to the base of the driver transistor, a cascode transistor having a base, collector and emitter, the emitter of the cascode transistor being coupled to the collector of the driver transistor, an RF output port coupled to the collector of the cascode transistor, and a coupling path connecting the base of the cascode transistor to the emitter of the cascode transistor, the coupling path including a capacitor.

Abstract: A radio-frequency module comprises a low-noise amplifier including a common source transistor having a gate node that receives a radio-frequency input signal and a drain node that transmits a combined radio-frequency output signal, and a correction signal input path configured to receive a correction signal and provide the correction signal to a source node of the common source transistor to generate, at least in part, the combined radio-frequency output signal.

Abstract: Circuits, devices and methods are disclosed, including a phase shifter configured to provide a bypass state, a single first-handed quarter-wave state, a double first-handed quarter-wave state, or a single second-handed quarter-wave state utilizing two or less inductors. In some implementations, a phase shifter is disclosed to provide a first node and a second node, a first switchable path having a first inductance and a second inductance arranged in series between the first and second nodes, a capacitive grounding path implemented on each side of each of the first and second inductances, at least one of the capacitive grounding paths configured as a switchable capacitive grounding path, and a reconfiguring circuit assembly configured to allow the phase shifter to provide a plurality of quadrant phase shifts utilizing the first and second inductances and the at least one switchable capacitive grounding path.

Abstract: Circuits, devices and methods are disclosed, including a phase shifter comprising a first node and a second node, and a first transmission line element having an inductance and a variable capacitance on each side of the inductance, the variable capacitance configured to provide a plurality of capacitance values to yield corresponding phase shift values based on an increment having a magnitude that is less than 90 degrees. In some implementations, the phase shifter further comprises a second transmission line element in series with the first transmission line element, the second transmission line element having an inductance and a variable capacitance on each side of the inductance configured to extend an overall phase shift range provided by the phase shifter.

Abstract: Disclosed are systems and method for controlling frequency synthesizers. A control system can be implemented in a phase-locked loop (PLL), such as a Frac-N PLL of a frequency synthesizer, to reduce or eliminate reference spurs. In some embodiments, such a control system can include a phase detector configured to receive a reference signal and a feedback signal. The phase detector can be configured to generate a first signal representative of a phase difference between the reference signal and the feedback signal. The control system can further include a charge pump configured to generate a compensation signal based on the first signal. The control system can further includes an oscillator configured to generate an output signal based on the compensation signal. The compensation signal can be configured to reduce or substantially eliminate one or more reference spurs associated with the frequency synthesizer.

Abstract: Disclosed are circuits and method for reducing or eliminating reference spurs in frequency synthesizers. In some implementations, a phase-locked loop (PLL) such as a Frac-N PLL of a frequency synthesizer can include a phase frequency detector (PFD) configured to receive a reference signal and a feedback signal. The PFD can be configured to generate a first signal representative of a phase difference between the reference signal and the feedback signal. The PLL can further include a compensation circuit configured to generate a compensation signal based on the first signal. The PLL can further includes a voltage-controlled oscillator (VCO) configured to generate an output signal based on the compensation signal. The compensation signal can include at least one feature for substantially eliminating one or more reference spurs associated with the PLL.

Abstract: A method and system provide a complete energy analytical model. An input model is acquired and consists of a combination of architectural building elements (ABEs) and conceptual massing elements (CMEs). The input model is pre-processed by extracting information from both the ABEs and the CMEs, and constructing virtual elements that encapsulate the extracted information. A discrete set of points in three-dimensional (3D) space that is distributed over boundary faces of the ABEs or CMEs is determined. The discrete set of points is used to provide a representation of the input model that is used in combination with a 3D cubical grid (a voxel grid) to analyze a spatial structure of the input model. A two-dimensional (2D) discrete approximation of the geometry of the input model is used to determine surfaces of the energy analytical model which is then output.

Abstract: Disclosed are circuits and method for reducing or eliminating reference spurs in frequency synthesizers. In some implementations, a phase-locked loop (PLL) such as a Frac-N PLL of a frequency synthesizer can include a phase frequency detector (PFD) configured to receive a reference signal and a feedback signal. The PFD can be configured to generate a first signal representative of a phase difference between the reference signal and the feedback signal. The PLL can further include a compensation circuit configured to generate a compensation signal based on the first signal. The PLL can further includes a voltage-controlled oscillator (VCO) configured to generate an output signal based on the compensation signal. The compensation signal can include at least one feature for substantially eliminating one or more reference spurs associated with the PLL.

Abstract: Disclosed are systems and method for controlling frequency synthesizers. A control system can be implemented in a phase-locked loop (PLL), such as a Frac-N PLL of a frequency synthesizer, to reduce or eliminate reference spurs. In some embodiments, such a control system can include a phase detector configured to receive a reference signal and a feedback signal. The phase detector can be configured to generate a first signal representative of a phase difference between the reference signal and the feedback signal. The control system can further include a charge pump configured to generate a compensation signal based on the first signal. The control system can further includes an oscillator configured to generate an output signal based on the compensation signal. The compensation signal can be configured to reduce or substantially eliminate one or more reference spurs associated with the frequency synthesizer.

Abstract: Disclosed are circuits and method for reducing or eliminating reference spurs in frequency synthesizers. In some implementations, a phase-locked loop (PLL) such as a Frac-N PLL of a frequency synthesizer can include a phase frequency detector (PFD) configured to receive a reference signal and a feedback signal. The PFD can be configured to generate a first signal representative of a phase difference between the reference signal and the feedback signal. The PLL can further include a compensation circuit configured to generate a compensation signal based on the first signal. The PLL can further includes a voltage-controlled oscillator (VCO) configured to generate an output signal based on the compensation signal. The compensation signal can include at least one feature for substantially eliminating one or more reference spurs associated with the PLL.

Abstract: Disclosed are circuits and method for reducing or eliminating reference spurs in frequency synthesizers. In some implementations, a phase-locked loop (PLL) such as a Frac-N PLL of a frequency synthesizer can include a phase frequency detector (PFD) configured to receive a reference signal and a feedback signal. The PFD can be configured to generate a first signal representative of a phase difference between the reference signal and the feedback signal. The PLL can further include a compensation circuit configured to generate a compensation signal based on the first signal. The PLL can further includes a voltage-controlled oscillator (VCO) configured to generate an output signal based on the compensation signal. The compensation signal can include at least one feature for substantially eliminating one or more reference spurs associated with the PLL.