Abstract: It has been found that integrated packages having dies with at least 10 bonding pads separated by a pitch of 65 ?m or less are susceptible to corrosion upon wire bonding to these pads and subsequent encapsulation in a passivating material. In particular, crevices are potentially formed between the bonding wire and bonding pad that are not passivated and that promote corrosion. Avoidance of crevice formation through, for example, appropriately choosing the bonding pad and wire configuration substantially avoids such corrosion.

Abstract: Typical testing of solder joints, (e.g. joints at printed circuit board pads) has not proven totally predictive of the ultimate performance of such joints. It has been found that this lack of reliability is, at least in part, due to the tendency during testing for these pads to lose adhesion to, or delaminate from, the underlying substrate. In contrast, such occurrence is not typical of phenomena induced during typical device usage. To remove this source of unreliability, a test structure is made together with the manufacturing device lot. The same pad processing is used and the pad size is substantially enlarged in the test structure. The test structure is employed to predict performance of devices in the lot and then the lot is processed accordingly.

Abstract: Many electronic entities such as integrated circuits and discrete power devices have contact pads formed from successively deposited layers of nickel and a second metal such as gold. The resulting pad structure is used to make external electrical connection such as solder connection. Problems associated with failure of such connections are avoidable by inspecting the surface of the nickel layer for excessive small particle formation.

Abstract: Assemblies involving integrated circuit dies (e.g. packaged integrated circuits) and packaged dies electrically connected to circuit boards at times mechanically fail at conducting pads used for electrical interconnection. Such failure is mitigated by underlying appropriate pads with a compliant region having specific characteristics.

Abstract: Typical testing of solder joints, (e.g. joints at printed circuit board pads) has not proven totally predictive of the ultimate performance of such joints. It has been found that this lack of reliability is, at least in part, due to the tendency during testing for these pads to lose adhesion to, or delaminate from, the underlying substrate. In contrast, such occurrence is not typical of phenomena induced during typical device usage. To remove this source of unreliability, a test structure is made together with the manufacturing device lot. The same pad processing is used and the pad size is substantially enlarged in the test structure. The test structure is employed to predict performance of devices in the lot and then the lot is processed accordingly.

Abstract: Many electronic entities such as integrated circuits and discrete power devices have contact pads formed from successively deposited layers of nickel and a second metal such as gold. The resulting pad structure is used to make external electrical connection such as solder connection. Problems associated with failure of such connections are avoidable by inspecting the surface of the nickel layer for excessive small particle formation.

Abstract: Assemblies involving integrated circuit dies (e.g. packaged integrated circuits) and packaged dies electrically connected to circuit boards at times mechanically fail at conducting pads used for electrical interconnection. Such failure is mitigated by underlying appropriate pads with a compliant region having specific characteristics.

Abstract: A semiconductor device package comprises a container including a base and sidewalls. The base is configured to support a semiconductor device chip, and a lead frame extends through at least one of the sidewalls. A portion of the lead frame within the sidewall has at least one aperture penetrating into the lead frame. The sidewall material extends into the aperture, thereby forming a strong interfacial bond that provides a low leakage, sidewall-lead-frame interface. The base has a reentrant feature that is positioned within the thickness of at least one of the sidewalls and engages the at least one sidewall, thereby forming a low leakage base-sidewall interface. The top surface of the base has a groove that is positioned within the thickness of at least one of the sidewalls and engages the at least one sidewall, thereby enhancing the low leakage base-sidewall interface.

Abstract: It has been found that integrated packages having dies with at least 10 bonding pads separated by a pitch of 65 ?m or less are susceptible to corrosion upon wire bonding to these pads and subsequent encapsulation in a passivating material. In particular, crevices are potentially formed between the bonding wire and bonding pad that are not passivated and that promote corrosion. Avoidance of crevice formation through, for example, appropriately choosing the bonding pad and wire configuration substantially avoids such corrosion.

Abstract: A process includes annealing one or more plated conductive leads at a predetermined temperature. The one or more plated conductive leads are plated with one or more layers, where each layer comprises a material. The predetermined temperature is greater than or equal to approximately a melting point of one of the materials. The annealing can reduce growth formations, such as whiskers, on the one or more conductive leads. Lead frames and other devices having plated conductive leads may be subjected to the process, and the resultant plated conductive leads will have fewer growth formations than plated conductive leads not subjected to the process. The plated conductive leads may be trimmed and formed prior to or after the anneal.

Abstract: An optical package includes one or more MEMS mirrors to provide alignment between internal optical components and the signal port(s) on the package (where one or more ports may include optical fiber attachments). Once the components are placed in the package, an electrical signal is used to adjust the deflection profile of the appropriately positioned MEMS mirror(s) until maximum coupling between the internal components and the fibers/ports is obtained. Advantageously, if later signal degradation occurs due to, for example, subsequent physical misalignment of the internal components, corrective electrical signal can be sent to the MEMS mirror(s) to provide correction and re-alignment without having to open the package and physically move the components.

Abstract: Device packages often include walls build on a heat sink that surrounds a device die that thermally interacts with the heat sink. Use of raised or depressed feature on said heat sink that contacts the walls improves the cohesiveness of the package. By appropriately positioning these features contaminant infusion into the package is improved without degrading cohesiveness.

Abstract: Devices such as amplifiers are built on a heat sink having a perimeter wall surrounding active electronic devices. Surprisingly formation of wire bonds to such devices tends to be degraded if they have an aspect ratio greater than 2:1. This problem is overcome by forming wire bonds before such walls have a height of 30 mils and after bond formation extending the walls to their final height.

Abstract: A semiconductor device package comprises a container including a base and sidewalls. The base is configured to support a semiconductor device chip, and a lead frame extends through at least one of the sidewalls. A portion of the lead frame within the sidewall has at least one aperture penetrating into the lead frame. The sidewall material extends into the aperture, thereby forming a strong interfacial bond that provides a low leakage, sidewall-lead-frame interface. The base has a reentrant feature that is positioned within the thickness of at least one of the sidewalls and engages the at least one sidewall, thereby forming a low leakage base-sidewalls interface. The top surface of the base has a groove that is positioned within the thickness of at least one of the sidewalls and engages the at least one sidewall, thereby enhancing the low leakage base-sidewall interface.

Abstract: Power transistor devices and techniques for reducing bowing in such devices are provided. In one aspect, a power transistor device is provided. The power transistor device comprises a substrate, a device film formed on the substrate and an adhesion layer formed on a side of the substrate opposite the device film, wherein at least a portion of the adhesion layer is at least partially segmented. The power transistor device thereby exhibits a reduced amount of bowing relative to an amount of bowing expected without the segmenting of the adhesion layer. The power transistor device may be part of an integrated circuit.

Abstract: An improved method and solder composition for kinetically controlled part bonding. The method involves applying at least a first chemical element layer of an intermetallic compound to a first part and applying at least a second chemical element layer of the intermetallic compound to a second part. The first and second parts are placed together so that the chemical element layers contact each other. The parts are heated from a storage temperature to a bonding temperature which is slightly above a first melting temperature that melts the chemical element layer of one of the first and second parts into a liquid mixture. The composition of liquid mixture varies with time during heating due to the formation of the intermetallic compound therein by progressive incorporation of the other one of the first and second chemical element layers into the mixture.

Abstract: Disclosed herein is a reinforcing system and method for reinforcing a contact pad of an integrated circuit. Specifically exemplified is a system and method that comprises a reinforcing structure interposed between a top contact pad layer and an underlying metal layer.

Abstract: An optical wire board which utilizes a silicon substrate as the base for both the optical subassembly and the electrical RF transmitting circuit. An optical fiber is preferably passively aligned to the active optical device mounted on the optical subassembly using a V-groove etched into the silicon (and may include a lens or other optical element positioned between the fiber and the active device). An integrated circuit for coupling the active optical device to external contacts is preferably flip-chip mounted to the silicon substrate upon pads disposed on precisely defined edges around a cavity etched beneath the circuit, the inclusion of the cavity beneath the electrical circuit functioning to minimize the dielectric loading effect of the silicon substrate on the integrated circuit.

Abstract: A process for forming a polyphenylene sulfide (PPS) component is disclosed. The PPS is molded at a temperature of about 110° C. to about 150° C. After molding, the PPS has a morphology that is at least fifty percent polycrystalline. The component is then annealed to further increase the polycrystalline portion of the PPS morphology. To effect this increase, the component is annealed at a temperature that is at least above the glass transition temperature of the molded PPS component but below its melting temperature. The component is used in optical applications and other applications in which alignment tolerances are small.

Abstract: A process for forming a polyphenylene sulfide (PPS) component is disclosed. The PPS is molded at a temperature of about 110° C. to about 150° C. After molding, the PPS has a morphology that is at least fifty percent polycrystalline. The component is then annealed to further increase the polycrystalline portion of the PPS morphology. To effect this increase, the component is annealed at a temperature that is at least above the glass transition temperature of the molded PPS component but below its melting temperature. The component is used in optical applications and other applications in which alignment tolerances are small.