Patents by Inventor John William Phillips

John William Phillips has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11136759
    Abstract: An example of support member is provided. The support member includes a plurality of elongated members connected to form a first elongated rigid structure. In addition, the support member includes a first elongated member of the plurality of elongated members disposed proximate to a first edge of the first elongated rigid structure with a first member top surface. The support member further includes a first stacking guide disposed on the first elongated member wherein a first attachment top surface is to slope toward the first member top surface. Also, the support member includes a second elongated member of the plurality of elongated members disposed proximate to a second edge of the first elongated rigid structure with a second member top surface. The second edge is opposite the first edge. The support member also includes a second stacking guide disposed on the second elongated member.
    Type: Grant
    Filed: December 5, 2019
    Date of Patent: October 5, 2021
    Assignee: STAGE LIGHTING PATENTS, LLC
    Inventor: John William Phillips
  • Publication number: 20210172172
    Abstract: An example of support member is provided. The support member includes a plurality of elongated members connected to form a first elongated rigid structure. In addition, the support member includes a first elongated member of the plurality of elongated members disposed proximate to a first edge of the first elongated rigid structure with a first member top surface. The support member further includes a first stacking guide disposed on the first elongated member wherein a first attachment top surface is to slope toward the first member top surface. Also, the support member includes a second elongated member of the plurality of elongated members disposed proximate to a second edge of the first elongated rigid structure with a second member top surface. The second edge is opposite the first edge. The support member also includes a second stacking guide disposed on the second elongated member.
    Type: Application
    Filed: December 5, 2019
    Publication date: June 10, 2021
    Applicant: Christie Lites Enterprises USA
    Inventor: John William PHILLIPS
  • Publication number: 20170066196
    Abstract: A system configured to facilitate formation of additive manufacturing objects is described. The system may obtain a virtual three-dimensional representation of an object, determine positions for a layered series of contour lines for the object based on the three-dimensional representation; and determine individual wave functions that correspond to a given contour line for a given layer. An individual wave function may indicate a three or more dimensional waveform pathway for an additive manufacturing platform to follow within a given layer when forming the given layer of the object. The system may control movement of the additive manufacturing platform to additively manufacture the object following waveform pathways. Controlling movement of the additive manufacturing platform based on the wave functions facilitates additively manufacturing objects without a need for support material for overhanging features.
    Type: Application
    Filed: September 6, 2016
    Publication date: March 9, 2017
    Inventors: Nigel Beard, Walter Edmondson, John William Phillips, Francis Anthony Bitonti, Lucy Beard
  • Patent number: 7353368
    Abstract: A method comprising fetching an input from at least one of a plurality of floating-point registers and detecting whether the input includes a token. If the token is detected in the input, checking what mode the processor is in. If the processor is in a first mode, processing the input to render an arithmetic result. If the processor is in a second mode, performing a token specific operation. And producing an output. The present invention also provides a processor comprising a first instruction set engine, a second instruction set engine, and a mode identifier. A plurality of floating-point registers are shared by the first instruction set engine and the second instruction set engine. A floating-point unit is coupled to the floating-point registers. The floating-point unit processes an input responsive to the mode identifier and the input to produce an output.
    Type: Grant
    Filed: February 15, 2000
    Date of Patent: April 1, 2008
    Assignee: Intel Corporation
    Inventors: Michael Chow, Elango Ganesan, John William Phillips, Nazar Abbas Zaidi
  • Publication number: 20030154366
    Abstract: A method comprising fetching an input from at least one of a plurality of floating-point registers and detecting whether the input includes a token. If the token is detected in the input, checking what mode the processor is in. If the processor is in a first mode, processing the input to render an arithmetic result. If the processor is in a second mode, performing a token specific operation. And producing an output. The present invention also provides a processor comprising a first instruction set engine, a second instruction set engine, and a mode identifier. A plurality of floating-point registers are shared by the first instruction set engine and the second instruction set engine. A floating-point unit is coupled to the floating-point registers. The floating-point unit processes an input responsive to the mode identifier and the input to produce an output.
    Type: Application
    Filed: February 15, 2000
    Publication date: August 14, 2003
    Inventors: Michael Chow, Elango Ganesan, John William Phillips, Nazar Abbas Zaidi
  • Patent number: 6219684
    Abstract: The present invention is a method and apparatus for rounding a result operand of a floating-point (FP) operation which causes an underflow. The FP operation is recomputed using a truncate rounding mode to generate an underflowed operand. The underflowed operand is denormalized and providing characteristic bits. A rounding bit is generated based on the characteristic bits. The rounding bit is merged with the denormalized operand to generate the rounded result operand.
    Type: Grant
    Filed: September 30, 1998
    Date of Patent: April 17, 2001
    Assignee: Intel Corporation
    Inventors: Rahul Saxena, John William Phillips
  • Patent number: 6038652
    Abstract: The present invention is a method and apparatus for reporting exception in a single instruction multiple data (SIMD) processor in computing an arithmetic function for a plurality of argument data. The SIMD processor is configured for processing N elements simultaneously. A sequence of instructions is re-arranged to allocate the plurality of argument data in the N elements. The N elements are processed simultaneously. The exceptions for N elements are detected simultaneously. The detected exceptions are then combined to generate a global exception.
    Type: Grant
    Filed: September 30, 1998
    Date of Patent: March 14, 2000
    Assignee: Intel Corporation
    Inventors: John William Phillips, Rahul Saxena