Patents by Inventor John William Tiede

John William Tiede has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5973980
    Abstract: An on-chip voltage regulator for controlling a gate of a regulator transistor having a first terminal coupled to receive an external power supply voltage and a second terminal coupled to provide a regulated voltage level to an internal circuit formed on a chip on which the on-chip voltage regulator is formed. The on-chip voltage regulator includes circuitry for detecting when a high current load to which the second terminal of the regulator transistor is coupled is activated. A control transistor is provided having a first terminal coupled to receive the external power supply voltage, a second terminal coupled to the gate of the regulator transistor, and a gate responsive to the means for detecting. In operation, a control voltage with an overshoot portion having preselected duration is generated on the gate of the regulator transistor in response to the activation of the high current load.
    Type: Grant
    Filed: July 23, 1998
    Date of Patent: October 26, 1999
    Assignees: United Memories, Inc., Nippon Steel Semiconductor Corporation
    Inventors: John William Tiede, Jon Allan Faue
  • Patent number: 5900021
    Abstract: A configurable input device for an integrated circuit having a plurality of input pads, the input device including a plurality of buffers, where each buffer is associated with one of the input pads. Each buffer receives a mode select signal and the buffer is responsive to the mode select signal to place the buffer in an enabled mode or a disabled mode. A receiver portion within each buffer is coupled to the associated input pad. The receiver portion pulls the associated input pad to a preselected logic state while the buffer is in the disabled mode. An output driver within each buffer generates an output signal responsive to a signal on the associated input pad while the buffer is in the enable mode and provides a high impedance while the buffer is in the disabled mode. An output node is coupled to the output drivers of the plurality of buffers.
    Type: Grant
    Filed: April 4, 1997
    Date of Patent: May 4, 1999
    Assignees: United Memories, Inc., Nippon Steel Semiconductor Corporation
    Inventors: John William Tiede, Jon Allan Faue
  • Patent number: 5818291
    Abstract: An on-chip voltage regulator for controlling a gate of a regulator transistor having a first terminal coupled to receive an external power supply voltage and a second terminal coupled to provide a regulated voltage level to an internal circuit formed on a chip on which the on-chip voltage regulator is formed. The on-chip voltage regulator includes circuitry for detecting when a high current load to which the second terminal of the regulator transistor is coupled is activated. A control transistor is provided having a first terminal coupled to receive the external power supply voltage, a second terminal coupled to the gate of the regulator transistor, and a gate responsive to the means for detecting. In operation, a control voltage with an overshoot portion having preselected duration is generated on the gate of the regulator transistor in response to the activation of the high current load.
    Type: Grant
    Filed: April 4, 1997
    Date of Patent: October 6, 1998
    Assignee: United Memories, Inc.
    Inventors: John William Tiede, Jon Allan Faue