Abstract: In one set of embodiments, a power management system comprises two or more devices, such as POL devices, configured to transmit and receive data over a shared bus, such as an I2C bus, according to the bus protocol of the shared bus. Each device may be configured with at least one respective address register, which may be programmed with an address uniquely identifying the device, and a mask register that may be configured to mask select bits of the respective address register, thereby enabling the device to identify device groups. In one embodiment, one of the devices identifying itself as a master device may distribute information to any of the other devices by transmitting the information, which may include commands and/or data, to itself, in effect targeting the address programmed into its own address register.

Abstract: A Device-to-Device Communication Bus protocol may facilitate transmission of a two to four byte packet by any device sharing the bus. All devices on the bus may monitor the bus, receiving all packets transmitted by other devices and recognizing when they may initiate transmission. The first byte of the packet may be an Address byte uniquely identifying the sender and allowing hardware arbitration to uniquely select one of any number of senders who may wish to transmit and begin transmission simultaneously. Arbitration may take place during transmission of the Address byte, with the transmitting device monitoring a bus bit value as it is transmitting the Address byte. If the data value observed by the transmitting device doesn't match the transmitting device's desired transmit value, the transmitting device may recognize loss of arbitration and suspend transmission to retry once the packet is complete. The receive function in every device may accept the packet as a normal received packet.

Abstract: A power management system may comprise two or more POL regulators configured to transmit and receive data over a shared bus according to either a proprietary or a common bus protocol. Each POL regulator may be identified by a unique address that is part of an address group, and may be configured via pin strapping to be able to perform a variety of power management functions. Any one of the POL regulators within the address group may become a bus master and transmit information to the shared bus by addressing itself. The other POL regulators in the address group may monitor the shared bus for events, and may respond to the transmitted information according to their address, their configuration, and the transmitted information. The response may include the POL regulators performing one or more power management functions, including adjusting their respective output voltages.

Abstract: A power management system may comprise two or more POL regulators configured to transmit and receive data over a shared bus according to either a proprietary or a common bus protocol. Each POL regulator may be identified by a unique address that is part of an address group, and may be configured via pin strapping to be able to perform a variety of power management functions. Any one of the POL regulators within the address group may become a bus master and transmit information to the shared bus by addressing itself The other POL regulators in the address group may monitor the shared bus for events, and may respond to the transmitted information according to their address, their configuration, and the transmitted information. The response may include the POL regulators performing one or more power management functions, including adjusting their respective output voltages.

Abstract: A power management system may comprise two or more POL regulators configured to transmit and receive data over a shared bus according to either a proprietary or a common bus protocol. Each POL regulator may be identified by a unique address that is part of an address group, and may be configured via pin strapping to be able to perform a variety of power management functions. Any one of the POL regulators within the address group may become a bus master and transmit information to the shared bus by addressing itself. The other POL regulators in the address group may monitor the shared bus for events, and may respond to the transmitted information according to their address, their configuration, and the transmitted information. The response may include the POL regulators performing one or more power management functions, including adjusting their respective output voltages.

Abstract: A power management system may be configured to allow digital information relating to the power management functions of sequencing and fault spreading to be passed between POL regulators using a standard multi-master multi-slave interface such as I2C bus interface or SMBus interface. POL regulators may be configured via pin strapping, and coupled to a serial data bus where they may monitor bus transactions initiated by other similar POL regulators. Each POL regulator may respond to the bus transactions initiated by other POL regulators according to its configuration, and may perform a variety of tasks associated with sequencing and fault spreading in addition to regulating its own voltage output. When configured with a standard multi-master/multi-slave interface such as an I2C bus interface or SMBus interface, the POL regulators may report information to multiple other POL regulators while maintaining compatibility with non-POL devices also connected to the bus.

Abstract: In one set of embodiments, a power management system comprises two or more devices, such as POL devices, configured to transmit and receive data over a shared bus, such as an I2C bus, according to the bus protocol of the shared bus. Each device may be configured with at least one respective address register, which may be programmed with an address uniquely identifying the device, and a mask register that may be configured to mask select bits of the respective address register, thereby enabling the device to identify device groups. In one embodiment, one of the devices identifying itself as a master device may distribute information to any of the other devices by transmitting the information, which may include commands and/or data, to itself, in effect targeting the address programmed into its own address register.

Abstract: A Device-to-Device Communication Bus protocol may facilitate transmission of a two to four byte packet by any device sharing the bus. All devices on the bus may monitor the bus, receiving all packets transmitted by other devices and recognizing when they may initiate transmission. The first byte of the packet may be an Address byte uniquely identifying the sender and allowing hardware arbitration to uniquely select one of any number of senders who may wish to transmit and begin transmission simultaneously. Arbitration may take place during transmission of the Address byte, with the transmitting device monitoring a bus bit value as it is transmitting the Address byte. If the data value observed by the transmitting device doesn't match the transmitting device's desired transmit value, the transmitting device may recognize loss of arbitration and suspend transmission to retry once the packet is complete. The receive function in every device may accept the packet as a normal received packet.

Abstract: A method and apparatus for scheduling packets using a pre-sort deficit round-robin method. Scheduling decisions for packets are made when packets are received, and entries for the received packets are stored in a pre-sorted scheduling array. A packet is transmitted by dequeuing the packet from the pre-sorted scheduling array.

Abstract: A method and apparatus for scheduling packets using a pre-sort scheduling array having one or more smoothing registers. The scheduling array includes a number of round buffers, each round buffer having an associated smoothing register. To schedule a packet for transmission, the packet's transmission round and relative position within that round are determined, and an identifier for the packet is placed at the appropriate position within the scheduling array. A bit of the associated smoothing register is set, the set bit corresponding to the entry receiving the packet identifier. During transmission, the set bits of the smoothing register associated with a current round buffer are read to identify packets that are to be dequeued.

Abstract: In general, in one aspect, the disclosure describes a method of processing bits of a frame. The method includes accessing a subset of bits of a frame and based, at least in part, on the subset of bits, determining an address of an instruction within a set of instructions that perform at least one framing operation on the bits. The method executes instructions at the determined instruction address.

Abstract: According to some embodiments, a method determining a number of stages associated with an instruction to be executed via a processor pipeline, determining a number of stages associated with a subsequent instruction, and stalling the pipeline based on the number of stages associated with the instruction to be executed and the number of stages associated with the subsequent instruction is provided.

Abstract: A programmed state processing machine architecture and method that provides improved efficiency for processing data manipulation tasks. In one embodiment, the processing machine comprises a control engine and a plurality coprocessors, a data memory, and an instruction memory. A sequence of instructions having a plurality of portions are issued by the instruction memory, wherein the control engine and each of the processors is caused to perform a specific task based on the portion of the instructions designated for that component. Accordingly, a data manipulation task can be divided into a plurality of subtasks that are processed in parallel by respective processing components in the architecture.

Abstract: A programmable processing system that executes multiple instruction contexts includes an instruction memory for storing instructions that are executed by the system, fetch logic for determining an address of an instruction, with the fetch logic including scheduling logic that schedules execution of the instruction contexts based on condition signals indicating an availability of a hardware resource, with the condition signals being divided into groups of condition signals, which are sampled in turn by the scheduling logic to provide a plurality of scan sets of sampled conditions.

Abstract: According to some embodiments, storage registers are provided for a processor pipeline.

Abstract: A Media Access Control (MAC) Bus interface definition and multiplexor scheme that may be implemented to provide chip layout-insensitive connections between a number of communication physical layer port entities and a single buffer manager or communications controller entity, utilizing a set of independent pipelined buses. The interface comprising three buses: A MAC In Data bus, a MAC Out Data bus, and a MAC Out Message bus. Each bus can operated with an independent set of timing signals to enable data transfers between a system side block and one or more network side blocks. The multiplexor scheme provides a multiplexor for each of the MAC buses, and enables a single system side block to connect to multiple network side blocks. The multiplexors may be also be cascaded.

Abstract: A method and apparatus for scheduling packets using a pre-sort scheduling array having one or more smoothing registers. The scheduling array includes a number of round buffers, each round buffer having an associated smoothing register. To schedule a packet for transmission, the packet's transmission round and relative position within that round are determined, and an identifier for the packet is placed at the appropriate position within the scheduling array. A bit of the associated smoothing register is set, the set bit corresponding to the entry receiving the packet identifier. During transmission, the set bits of the smoothing register associated with a current round buffer are read to identify packets that are to be dequeued.

Abstract: A method and apparatus for scheduling packets using one or more pre-sort scheduling arrays. Scheduling decisions for packets are made when packets are received, and entries for the received packets are stored in a pre-sorted scheduling array. Packets may be scheduled according to a non-work conserving technique, or packets may be scheduled according to a work conserving technique. A packet is transmitted by dequeuing the packet from a pre-sorted scheduling array.

Abstract: A programmable processing system that executes multiple instruction contexts includes an instruction memory for storing instructions that are executed by the system, fetch logic for determining an address of an instruction, with the fetch logic including scheduling logic that schedules execution of the instruction contexts based on condition signals indicating an availability of a hardware resource, with the condition signals being divided into groups of condition signals, which are sampled in turn by the scheduling logic to provide a plurality of scan sets of sampled conditions.

Abstract: A processing system that executes multiple instruction contexts includes an instruction memory for storing instructions that are executed by the system, a processor unit executing the instructions in a pipelined fashion, a plurality of context registers for storing instructions and instruction addresses for contexts to be executed and fetch logic for selecting an address from one of the context registers and for selecting an instruction from a second of the context registers for execution substantially simultaneously for each cycle of execution of processor unit.