Patents by Inventor John Wiss

John Wiss has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8199779
    Abstract: Apparatus, system and method for synchronizing one or more clocks across a communication link. A slave clock may be synchronized to a master clock by means of a synchronization signal sent from the master to the slave clock side of the link. The synchronization signal may be an expected signal pattern sent at intervals expected by the slave side. The slave clock may correlate received signals with a representation of the expected synchronization signal to produce a correlation sample sequence at a first sample rate which is related as n times the slave clock rate. The synchronization signal receipt time indicated by the correlation sample sequence may be refined by interpolating the correlation sample sequence around a best correlation sample to locate a best interpolation at an interpolation resolution smaller than the sample resolution. The best interpolation may in turn be further refined by estimating between interpolator outputs adjacent to the best interpolation output.
    Type: Grant
    Filed: February 4, 2011
    Date of Patent: June 12, 2012
    Assignee: Wi-LAN, Inc.
    Inventors: Pranesh Sinha, Sharon Akler, Yair Bourlas, Timothy Leo Gallagher, Sheldon L. Gilbert, Stephen C. Pollmann, Frederick W. Price, Blaine C. Readler, John Wiss, Eli Arviv
  • Publication number: 20110122981
    Abstract: Apparatus, system and method for synchronizing one or more clocks across a communication link. A slave clock may be synchronized to a master clock by means of a synchronization signal sent from the master to the slave clock side of the link. The synchronization signal may be an expected signal pattern sent at intervals expected by the slave side. The slave clock may correlate received signals with a representation of the expected synchronization signal to produce a correlation sample sequence at a first sample rate which is related as n times the slave clock rate. The synchronization signal receipt time indicated by the correlation sample sequence may be refined by interpolating the correlation sample sequence around a best correlation sample to locate a best interpolation at an interpolation resolution smaller than the sample resolution. The best interpolation may in turn be further refined by estimating between interpolator outputs adjacent to the best interpolation output.
    Type: Application
    Filed: February 4, 2011
    Publication date: May 26, 2011
    Applicant: WI-LAN, INC.
    Inventors: Pranesh Sinha, Sharon Akler, Yair Bourlas, Timothy Leo Gallagher, Sheldon L. Gilbert, Stephen C. Pollmann, Frederick W. Price, Blaine C. Readler, John Wiss, Eli Arviv
  • Patent number: 7907640
    Abstract: A slave clock may be synchronized to a master clock by means of a synchronization signal sent from the master to the slave clock side of the link. The synchronization signal may be an expected signal pattern sent at intervals expected by the slave side. The slave clock may correlate received signals with a representation of the expected synchronization signal to produce a correlation sample sequence at a first sample rate which is related as n times the slave clock rate. A best interpolation may in turn be further refined by estimating between interpolator outputs adjacent to the best interpolation output. The synchronization signal receipt time thus determined is compared to the expected time based upon the slave clock, which is adjusted until the times match. The best interpolation may in turn be further refined by estimating between interpolator outputs adjacent to the best interpolation output.
    Type: Grant
    Filed: July 23, 2009
    Date of Patent: March 15, 2011
    Assignee: Wi-LAN, Inc.
    Inventors: Pranesh Sinha, Sharon Akler, Yair Bourlas, Timothy Leo Gallagher, Sheldon L. Gilbert, Stephen C. Pollmann, Frederick W. Price, Blaine C. Readler, John Wiss, Eli Arviv
  • Publication number: 20090279652
    Abstract: Apparatus, system and method for synchronizing one or more clocks across a communication link. A slave clock may be synchronized to a master clock by means of a synchronization signal sent from the master to the slave clock side of the link. The synchronization signal may be an expected signal pattern sent at intervals expected by the slave side. The slave clock may correlate received signals with a representation of the expected synchronization signal to produce a correlation sample sequence at a first sample rate which is related as n times the slave clock rate. The synchronization signal receipt time indicated by the correlation sample sequence may be refined by interpolating the correlation sample sequence around a best correlation sample to locate a best interpolation at an interpolation resolution smaller than the sample resolution. The best interpolation may in turn be further refined by estimating between interpolator outputs adjacent to the best interpolation output.
    Type: Application
    Filed: July 23, 2009
    Publication date: November 12, 2009
    Applicant: WI-LAN, INC.
    Inventors: Pranesh Sinha, Sharon Akler, Yair Bourlas, Timothy Leo Gallagher, Sheldon L. Gilbert, Stephen C. Pollmann, Frederick W. Price, Blaine C. Readler, John Wiss, Eli Arviv
  • Patent number: 7583705
    Abstract: One or more clocks are synchronized across a communication link using a synchronization signal sent from a master to a slave clock. The synchronization signal may be an expected signal pattern sent at intervals expected by the slave. The slave clock may correlate received signals with a representation of the expected synchronization signal to produce a correlation sample sequence at a first sample rate. The synchronization signal receipt time is compared to the expected time and the slave clock is adjusted until the times match. Master and slave clocks synchronized across the communication link constitute a noncommon clock which may be compared on each side of the link to secondary independent clocks. The secondary independent clocks may be separately synchronized by adjusting one to have the same difference from its local noncommon clock as the secondary clock on the other side of the link has from its local noncommon clock.
    Type: Grant
    Filed: June 29, 2005
    Date of Patent: September 1, 2009
    Assignee: Wi-LAN, Inc.
    Inventors: Pranesh Sinha, Sharon Akler, Yair Bourlas, Timothy Leo Gallagher, Sheldon L. Gilbert, Stephen C. Pollmann, Frederick W. Price, Blaine C. Readler, John Wiss, Eli Arviv
  • Publication number: 20070002987
    Abstract: Apparatus, system and method for synchronizing one or more clocks across a communication link. A slave clock may be synchronized to a master clock by means of a synchronization signal sent from the master to the slave clock side of the link. The synchronization signal may be an expected signal pattern sent at intervals expected by the slave side. The slave clock may correlate received signals with a representation of the expected synchronization signal to produce a correlation sample sequence at a first sample rate which is related as n times the slave clock rate. The synchronization signal receipt time indicated by the correlation sample sequence may be refined by interpolating the correlation sample sequence around a best correlation sample to locate a best interpolation at an interpolation resolution smaller than the sample resolution. The best interpolation may in turn be further refined by estimating between interpolator outputs adjacent to the best interpolation output.
    Type: Application
    Filed: June 29, 2005
    Publication date: January 4, 2007
    Inventors: Pranesh Sinha, Sharon Akler, Yair Bourlas, Timothy Gallagher, Sheldon Gilbert, Stephen Pollmann, Frederick Price, Blaine Readler, John Wiss, Eli Arviv
  • Publication number: 20060072656
    Abstract: The signal-to-noise ratio of a demodulated received signal is estimated by measuring the error vector magnitude (EVM) of the demodulated signal; and processing the measured EVM in combination with a correction term to estimate the signal-to-noise ratio of the demodulated signal. The correction term is a polynomial function of the measured EVM. The signal-to-noise ratio is estimated in accordance with the formula: E S N 0 ? 10 · LOG 10 ? ( ? · ? E S ? 4 ? [ ? ^ z + C ? ( ? ^ z ) ] 2 ) ? ? ? ( dB ) wherein {circumflex over (?)}z is the measured EVM based on the mean of a Rayleigh density of EVM measurements; and C is the correction term. For QPSK modulated signals, C is calculated in accordance with the formula: CQPSK({circumflex over (?)}z)?2.71×10?3{circumflex over (?)}z3?7.54×10?2{circumflex over (?)}z2+0.7{circumflex over (?)}z?2.25 For BPSK modulated signals, C is calculated in accordance with the formula: CBPSK({circumflex over (?)}z)?1.
    Type: Application
    Filed: October 1, 2004
    Publication date: April 6, 2006
    Inventors: John Wiss, Timothy Blalock
  • Patent number: 6944188
    Abstract: Apparatus, system and method for synchronizing one or more clocks across a communication link. A slave clock may be synchronized to a master clock by means of a synchronization signal sent from the master to the slave clock side of the link. The synchronization signal may be an expected signal pattern sent at intervals expected by the slave side. The slave clock may correlate received signals with a representation of the expected synchronization signal to produce a correlation sample sequence at a first sample rate which is related as n times the slave clock rate. The synchronization signal receipt time indicated by the correlation sample sequence may be refined by interpolating the correlation sample sequence around a best correlation sample to locate a best interpolation at an interpolation resolution smaller than the sample resolution. The best interpolation may in turn be further refined by estimating between interpolator outputs adjacent to the best interpolation output.
    Type: Grant
    Filed: February 21, 2001
    Date of Patent: September 13, 2005
    Assignee: Wi-Lan, Inc.
    Inventors: Pranesh Sinha, Sharon Akler, Yair Bourlas, Timothy Leo Gallagher, Sheldon L. Gilbert, Stephen C. Pollmann, Frederick W. Price, Blaine C. Readler, John Wiss, Ell Arviv
  • Publication number: 20020114354
    Abstract: Apparatus, system and method for synchronizing one or more clocks across a communication link. A slave clock may be synchronized to a master clock by means of a synchronization signal sent from the master to the slave clock side of the link. The synchronization signal may be an expected signal pattern sent at intervals expected by the slave side. The slave clock may correlate received signals with a representation of the expected synchronization signal to produce a correlation sample sequence at a first sample rate which is related as n times the slave clock rate. The synchronization signal receipt time indicated by the correlation sample sequence may be refined by interpolating the correlation sample sequence around a best correlation sample to locate a best interpolation at an interpolation resolution smaller than the sample resolution. The best interpolation may in turn be further refined by estimating between interpolator outputs adjacent to the best interpolation output.
    Type: Application
    Filed: February 21, 2001
    Publication date: August 22, 2002
    Inventors: Pranesh Sinha, Sharon Akler, Yair Bourlas, Timothy Leo Gallagher, Sheldon L. Gilbert, Stephen C. Pollmann, Fredrick W. Price, Blaine C. Readler, John Wiss, Ell Arviv
  • Publication number: 20020097812
    Abstract: A first variable gain function is in series with an unbalanced in-phase component, and a circuit loop produces a first error signal which varies the first gain function such that its output is a signal which continuously converges toward a balanced in-phase component. A second variable gain function receives as input the unbalanced in-phase component, and a summing function in series with the unbalanced quadrature component algebraically adds the unbalanced quadrature component and the output of the second gain function. A second circuit loop produces a second error signal which varies the second gain function such that the output of the summing function is a signal which continuously converges toward a balanced quadrature component.
    Type: Application
    Filed: December 1, 2000
    Publication date: July 25, 2002
    Inventor: John Wiss