Patents by Inventor John Wuu
John Wuu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11869874Abstract: A stacked die system includes at least three dies. A first die has a same design as a second die. The first die includes a first circuit, and the second die includes a corresponding second circuit. A signal is received at the first die and sent to the third die via the second die. The signal is routed through either the first circuit or the second circuit but not both. Accordingly, an operation is performed on the signal prior to the signal reaching the third die but the operation is not performed by both the first circuit and the second circuit.Type: GrantFiled: December 14, 2020Date of Patent: January 9, 2024Assignee: Advanced Micro Devices, Inc.Inventors: John Wuu, David Johnson
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Patent number: 11822484Abstract: A cache includes an upstream port, a cache memory for storing cache lines each having a line width, and a cache controller. The cache controller is coupled to the upstream port and the cache memory. The upstream port transfers data words having a transfer width less than the line width. In response to a cache line fill, the cache controller selectively determines data bus inversion information for a sequence of data words having the transfer width, and stores the data bus inversion information along with selected inverted data words for the cache line fill in the cache memory.Type: GrantFiled: December 20, 2021Date of Patent: November 21, 2023Assignee: Advanced Micro Devices, Inc.Inventors: Vydhyanathan Kalyanasundharam, John Wuu, Chintan S. Patel
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Publication number: 20230268319Abstract: A semiconductor assembly includes a first die having a front side metallization layer. The semiconductor assembly also includes a second side having a front side metallization layer that is bonded to the front side metallization layer of the first die.Type: ApplicationFiled: October 14, 2022Publication date: August 24, 2023Inventors: RAHUL AGARWAL, RAJA SWAMINATHAN, JOHN WUU
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Publication number: 20230207527Abstract: Integrated circuits and integrated circuit dies include TSVs laid out in symmetrical patterns. Because of the symmetrical arrangement of the TSVs and associated routing patterns, an integrated circuit is able to support operation of multiple similar dies that are placed in different positions in the integrated circuit. This in turn simplifies the design and production of the multiple similar dies, thus reducing development and manufacturing costs for the corresponding integrated circuits.Type: ApplicationFiled: December 28, 2021Publication date: June 29, 2023Inventors: Wonjun JUNG, Jasmeet SINGH NARANG, Tyrone HUANG, Christopher KLEMENT, Alan D. SMITH, Edward CHANG, John WUU
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Publication number: 20230195642Abstract: A cache includes an upstream port, a cache memory for storing cache lines each having a line width, and a cache controller. The cache controller is coupled to the upstream port and the cache memory. The upstream port transfers data words having a transfer width less than the line width. In response to a cache line fill, the cache controller selectively determines data bus inversion information for a sequence of data words having the transfer width, and stores the data bus inversion information along with selected inverted data words for the cache line fill in the cache memory.Type: ApplicationFiled: December 20, 2021Publication date: June 22, 2023Applicant: Advanced Micro Devices, Inc.Inventors: Vydhyanathan Kalyanasundharam, John Wuu, Chintan S. Patel
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Patent number: 11676659Abstract: A method for operating a memory device includes initiating an access operation to a corresponding row of an array of bit cells of the memory device. Responsive to an expansion mode signal having a first state, the method further includes dynamically operating each column of a plurality of columns of the array to access each bit cell of a corresponding row within the plurality of columns during the access operation. Alternatively, responsive to the expansion mode state signal having a second state different than the first state, the method includes dynamically operating each column of a first subset of columns of the plurality of columns to access each bit cell of a corresponding row within the first subset of columns during the access operation, and maintaining each column of a second subset of columns of the plurality of columns in a static state during the access operation.Type: GrantFiled: November 19, 2021Date of Patent: June 13, 2023Assignee: Advanced Micro Devices, Inc.Inventors: John Wuu, Martin Paul Piorkowski
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Publication number: 20230069294Abstract: A chip for multi-die communications couplings using a single bridge die, includes: a plurality of dies each including one or more functional circuit blocks; and a first bridge die directly communicatively coupling two or more pairs of dies of the plurality of dies.Type: ApplicationFiled: December 28, 2021Publication date: March 2, 2023Inventors: RAHUL AGARWAL, RAJA SWAMINATHAN, JOHN WUU, MIHIR PANDYA, SAMUEL D. NAFFZIGER
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Publication number: 20220189921Abstract: A stacked die system includes at least three dies. A first die has a same design as a second die. The first die includes a first circuit, and the second die includes a corresponding second circuit. A signal is received at the first die and sent to the third die via the second die. The signal is routed through either the first circuit or the second circuit but not both. Accordingly, an operation is performed on the signal prior to the signal reaching the third die but the operation is not performed by both the first circuit and the second circuit.Type: ApplicationFiled: December 14, 2020Publication date: June 16, 2022Inventors: John WUU, David JOHNSON
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Publication number: 20220148650Abstract: A method for operating a memory device includes initiating an access operation to a corresponding row of an array of bit cells of the memory device. Responsive to an expansion mode signal having a first state, the method further includes dynamically operating each column of a plurality of columns of the array to access each bit cell of a corresponding row within the plurality of columns during the access operation. Alternatively, responsive to the expansion mode state signal having a second state different than the first state, the method includes dynamically operating each column of a first subset of columns of the plurality of columns to access each bit cell of a corresponding row within the first subset of columns during the access operation, and maintaining each column of a second subset of columns of the plurality of columns in a static state during the access operation.Type: ApplicationFiled: November 19, 2021Publication date: May 12, 2022Inventors: John WUU, Martin Paul PIORKOWSKI
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Publication number: 20220059425Abstract: Various semiconductor chip devices with stacked chips are disclosed. In one aspect, a semiconductor chip device is provided. The semiconductor chip device includes a first semiconductor chip that has a floor plan with a high heat producing area and a low heat producing area. At least one second semiconductor chip is stacked on the low heat producing area. The semiconductor chip device also includes means for transferring heat from the high heat producing area.Type: ApplicationFiled: November 2, 2021Publication date: February 24, 2022Inventors: JOHN WUU, SAMUEL NAFFZIGER, PATRICK J. SHYVERS, MILIND S. BHAGAVAT, KAUSHIK MYSORE, BRETT P. WILKERSON
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Patent number: 11205477Abstract: A method for operating a memory device includes initiating an access operation to a corresponding row of an array of bit cells of the memory device. Responsive to an expansion mode signal having a first state, the method further includes dynamically operating each column of a plurality of columns of the array to access each bit cell of a corresponding row within the plurality of columns during the access operation. Alternatively, responsive to the expansion mode state signal having a second state different than the first state, the method includes dynamically operating each column of a first subset of columns of the plurality of columns to access each bit cell of a corresponding row within the first subset of columns during the access operation, and maintaining each column of a second subset of columns of the plurality of columns in a static state during the access operation.Type: GrantFiled: August 18, 2020Date of Patent: December 21, 2021Assignee: Advanced Micro Devices, Inc.Inventors: John Wuu, Martin Paul Piorkowski
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Patent number: 11189540Abstract: Various semiconductor chip devices with stacked chips are disclosed. In one aspect, a semiconductor chip device is provided. The semiconductor chip device includes a first semiconductor chip that has a floor plan with a high heat producing area and a low heat producing area. At least one second semiconductor chip is stacked on the low heat producing area. The semiconductor chip device also includes means for transferring heat from the high heat producing area.Type: GrantFiled: September 6, 2019Date of Patent: November 30, 2021Assignee: ADVANCED MICRO DEVICES, INC.Inventors: John Wuu, Samuel Naffziger, Patrick J. Shyvers, Milind S. Bhagavat, Kaushik Mysore, Brett P. Wilkerson
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Patent number: 11164807Abstract: Various semiconductor chip devices with stacked chips are disclosed. In one aspect, a semiconductor chip device is provided. The semiconductor chip device includes a first semiconductor chip that has a floor plan with a high heat producing area and a low heat producing area. At least one second semiconductor chip is stacked on the low heat producing area. The semiconductor chip device also includes means for transferring heat from the high heat producing area.Type: GrantFiled: September 6, 2019Date of Patent: November 2, 2021Assignee: ADVANCED MICRO DEVICES, INC.Inventors: John Wuu, Samuel Naffziger, Patrick J. Shyvers, Milind S. Bhagavat, Kaushik Mysore, Brett P. Wilkerson
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Publication number: 20210043250Abstract: A method for operating a memory device includes initiating an access operation to a corresponding row of an array of bit cells of the memory device. Responsive to an expansion mode signal having a first state, the method further includes dynamically operating each column of a plurality of columns of the array to access each bit cell of a corresponding row within the plurality of columns during the access operation. Alternatively, responsive to the expansion mode state signal having a second state different than the first state, the method includes dynamically operating each column of a first subset of columns of the plurality of columns to access each bit cell of a corresponding row within the first subset of columns during the access operation, and maintaining each column of a second subset of columns of the plurality of columns in a static state during the access operation.Type: ApplicationFiled: August 18, 2020Publication date: February 11, 2021Inventors: John WUU, Martin Paul PIORKOWSKI
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Patent number: 10839875Abstract: A timing circuit includes an input for receiving the control signal from a logic circuit operating with a first supply voltage and an output for supplying a control signal to a circuit operating with a second supply voltage different from the first supply voltage. The timing circuit also includes a plurality of delay elements connected in series between the input and output and supplied with the first supply voltage, and one or more NFET footer transistors that couple respective delay elements to a negative supply rail, the NFET footer transistors having the second supply voltage applied to their gates. A memory apparatus employing such a circuit is provided.Type: GrantFiled: March 29, 2019Date of Patent: November 17, 2020Assignee: Advanced Micro Devices, Inc.Inventors: Srinivas R. Sathu, John Wuu, Russell Schreiber, Martin Piorkowski
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Publication number: 20200312389Abstract: A timing circuit includes an input for receiving the control signal from a logic circuit operating with a first supply voltage and an output for supplying a control signal to a circuit operating with a second supply voltage different from the first supply voltage. The timing circuit also includes a plurality of delay elements connected in series between the input and output and supplied with the first supply voltage, and one or more NFET footer transistors that couple respective delay elements to a negative supply rail, the NFET footer transistors having the second supply voltage applied to their gates. A memory apparatus employing such a circuit is provided.Type: ApplicationFiled: March 29, 2019Publication date: October 1, 2020Applicant: Advanced Micro Devices, Inc.Inventors: Srinivas R. Sathu, John Wuu, Russell Schreiber, Martin Piorkowski
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Patent number: 10783953Abstract: A method for operating a memory device includes initiating an access operation to a corresponding row of an array of bit cells of the memory device. Responsive to an expansion mode signal having a first state, the method further includes dynamically operating each column of a plurality of columns of the array to access each bit cell of a corresponding row within the plurality of columns during the access operation. Alternatively, responsive to the expansion mode state signal having a second state different than the first state, the method includes dynamically operating each column of a first subset of columns of the plurality of columns to access each bit cell of a corresponding row within the first subset of columns during the access operation, and maintaining each column of a second subset of columns of the plurality of columns in a static state during the access operation.Type: GrantFiled: December 4, 2017Date of Patent: September 22, 2020Assignee: ADVANCED MICRO DEVICES, INC.Inventors: John Wuu, Martin Paul Piorkowski
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Patent number: 10644826Abstract: An integrated circuit includes first and second through-silicon via (TSV) circuits and a steering logic circuit. The first TSV circuit has a first TSV and a first multiplexer for selecting between a first TSV data signal received from the first TSV and a first local data signal for transmission to a first TSV output terminal. The second TSV circuit includes a second TSV and a second multiplexer for selecting between a second TSV data signal received from the second TSV and the first local data signal for transmission to a second TSV output terminal. The steering logic circuit controls the first multiplexer to select the first local data signal and the second multiplexer to select the second TSV data signal in a first mode, and the first multiplexer to select the first TSV data signal and the second multiplexer to select the first local data signal in a second mode.Type: GrantFiled: February 23, 2018Date of Patent: May 5, 2020Assignee: Advanced Micro Devices, Inc.Inventors: John Wuu, Samuel Naffziger, Michael K. Ciraula, Russell Schreiber
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Publication number: 20190393123Abstract: Various semiconductor chip devices with stacked chips are disclosed. In one aspect, a semiconductor chip device is provided. The semiconductor chip device includes a first semiconductor chip that has a floor plan with a high heat producing area and a low heat producing area. At least one second semiconductor chip is stacked on the low heat producing area. The semiconductor chip device also includes means for transferring heat from the high heat producing area.Type: ApplicationFiled: September 6, 2019Publication date: December 26, 2019Inventors: John Wuu, Samuel Naffziger, Patrick J. Shyvers, Milind S. Bhagavat, Kaushik Mysore, Brett P. Wilkerson
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Publication number: 20190393124Abstract: Various semiconductor chip devices with stacked chips are disclosed. In one aspect, a semiconductor chip device is provided. The semiconductor chip device includes a first semiconductor chip that has a floor plan with a high heat producing area and a low heat producing area. At least one second semiconductor chip is stacked on the low heat producing area. The semiconductor chip device also includes means for transferring heat from the high heat producing area.Type: ApplicationFiled: September 6, 2019Publication date: December 26, 2019Inventors: John Wuu, Samuel Naffziger, Patrick J. Shyvers, Milind S. Bhagavat, Kaushik Mysore, Brett P. Wilkerson