Abstract: Disclosed methods for lateral stacking of die can include positioning a first silicon chip of a semiconductor device horizontally with respect to a second silicon chip of the semiconductor device. The methods can additionally include positioning a third silicon chip of the semiconductor device vertically with respect to both the first silicon chip and the second silicon chip. The disclosed methods can also include electrically connecting the first silicon chip and the second silicon chip by the third silicon chip. Various other methods and systems are also disclosed.

Abstract: An exemplary apparatus includes a through-silicon via (TSV) and circuit that protects against the antenna effect and electrostatic discharge (ESD). The circuit can include a plurality of transistors whose gates are each electrically coupled to a signal that passes through the TSV. Various other apparatuses, systems, and methods are also disclosed.

Abstract: The disclosed device includes a bottom die layer having a bottom die and a bridge die adjacent to the bottom die. The device also includes a top die layer positioned on the bottom die layer and having a top die overlying at least a portion of the bottom die and overlying at least a portion of the bridge die. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: The disclosed device can include a bitcell array located on a first metal layer including a first subarray of bitcells and a second subarray of bitcells; a first write driver device coupled to the first subarray of bitcells from a first end of the first subarray; a second write driver device coupled to the second subarray of bitcells from a first end of the second subarray; a third write driver device coupled to the first subarray of bitcells from a second end of the first subarray; and a fourth write driver device coupled to the second subarray of bitcells from the second end of the second subarray. Various other devices, systems, and methods of manufacture are also disclosed.

Abstract: An integrated circuit die includes a set of electronic circuits disposed on a semiconductor material. The integrated circuit die also includes one or more through-silicon vias that vertically span the semiconductor material to transmit data signals. Additionally, the integrated circuit die includes a programmable delay element integrated with the set of electronic circuits on the semiconductor material and configured to delay data signals. Various other apparatuses, systems, and methods are also disclosed.

Abstract: An exemplary apparatus for uniquely identifying individual dies across die stacks includes a die stack and a plurality of signals arranged across the die stack. The plurality of signals are manipulated to form a unique identifier for each die included in the die stack. Various other apparatuses, systems, and methods are also disclosed.

Abstract: A bonded die assembly includes first conductive pads of a first substrate each bonded to respective second conductive pads of a second substrate, the first and second conductive pads arrayed at an inter-pad spacing, a plurality of active components located in the second substrate and arrayed at an inter-component spacing, and a metallization structure disposed between the first substrate and the second substrate, where the metallization structure is configured to decrease the inter-component spacing relative to the inter-pad spacing. The die assembly is characterized by an improved utilization of available device active area.

Abstract: A method for controlling power in 3D stacked die can include configuring a first die of a set of 3D stacked die to receive power from a power source, wherein the first die includes one or more field effect transistors configured to control the power. The method can also include configuring one or more power domains included in a second die of the set of 3D stacked die to receive the power that is controlled by the one or more field effect transistors included in the first die. Various other methods and systems are also disclosed.

Abstract: An exemplary apparatus for distributing die-specific signals across die stacks includes a die stack and a plurality of signals arranged in a sequence across the die stack. The plurality of signals shift positions in the sequence between a first die and a second die included in the die stack. Various other apparatuses, systems, and methods are also disclosed.

Abstract: A device can include a clock synthesizer and a clock signal multiplexer that is configured to provide a signal from the clock synthesizer as output during a test mode and to provide a forwarded clock signal as output during an operational mode. Various other devices, systems, and methods are also disclosed.

Abstract: A semiconductor device includes a first logic die comprising: a clock source configured to generate a clock signal; and a first clock mesh for receiving the clock signal from the clock source. The device includes a second logic die stacked over the first logic die, the second logic die comprising: a second clock mesh for receiving the clock signal from the clock source. The device includes a plurality of conductive connections between the first clock mesh and the second clock mesh to transmit the clock signal from the first clock mesh to the second clock mesh. Various other methods and systems are also disclosed.

Abstract: An exemplary apparatus includes a through-silicon via (TSV) and circuit that protects against the antenna effect and electrostatic discharge (ESD). The circuit can include a plurality of transistors whose gates are each electrically coupled to a signal that passes through the TSV. Various other apparatuses, systems, and methods are also disclosed.

Abstract: The disclosed device can include a bitcell array located on a first metal layer including a first subarray of bitcells and a second subarray of bitcells; a first write driver device coupled to the first subarray of bitcells from a first end of the first subarray; a second write driver device coupled to the second subarray of bitcells from a first end of the second subarray; a third write driver device coupled to the first subarray of bitcells from a second end of the first subarray; and a fourth write driver device coupled to the second subarray of bitcells from the second end of the second subarray. Various other devices, systems, and methods of manufacture are also disclosed.

Abstract: A hybrid bonding method includes fabricating plural semiconductor devices in a region of a bottom wafer adjacent to a front surface thereof, fusion bonding the front surface to a carrier substrate, thinning the bottom wafer opposite to the front surface to expose conductive regions of the semiconductor devices, forming a dielectric layer over a backside of the semiconductor devices, forming openings in the dielectric layer to expose the conductive regions, forming metal pads within the openings, dicing the bottom wafer and the carrier substrate to singulate the plural semiconductor devices, bonding the dielectric layer overlying the backside of the semiconductor devices to a dielectric layer overlying a front surface of a top wafer, bonding the metal pads within the openings in the dielectric layer to metal pads overlying the front surface of the top wafer, and removing the carrier substrate from the front surface of the bottom wafer.

Abstract: Various semiconductor chip devices with stacked chips are disclosed. In one aspect, a semiconductor chip device is provided. The semiconductor chip device includes a first semiconductor chip that has a floor plan with a high heat producing area and a low heat producing area. At least one second semiconductor chip is stacked on the low heat producing area. The semiconductor chip device also includes means for transferring heat from the high heat producing area.

Abstract: Integrated circuits and integrated circuit dies include TSVs laid out in symmetrical patterns. Because of the symmetrical arrangement of the TSVs and associated routing patterns, an integrated circuit is able to support operation of multiple similar dies that are placed in different positions in the integrated circuit. This in turn simplifies the design and production of the multiple similar dies, thus reducing development and manufacturing costs for the corresponding integrated circuits.

Abstract: A method for die pair partitioning can include providing a circuit die. The method can additionally include providing one or more additional circuit die having one or more fuses positioned therein, wherein the one or more fuses identify the circuit die. The method can also include connecting the one or more additional circuit die to the circuit die. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: A method for die pair partitioning can include providing a circuit die that has a metal stack and that includes a majority of logic transistors of an integrated circuit. The method can also include providing one or more additional circuit die that have one or more additional metal stacks of which at least one is connected to the metal stack of the circuit die and a majority of static random access memory and analog devices of the integrated circuit. The method can further include connecting at least one of the one or more additional metal stacks to the metal stack of the circuit die. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: A method for die pair partitioning can include providing a first circuit die having a first metal stack. The method can additionally include positioning a second circuit die having a second metal stack in a manner that places a temperature sensor in a transistor layer of the second circuit die in planar proximity to at least one hot spot located in an additional transistor layer of the first circuit die. The method can also include connecting the first metal stack of the first circuit die to the second metal stack of the second circuit die. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: A method for circuit die stacking can include providing a first circuit die having a first metal stack, wherein the first circuit die corresponds to a primary thermal source of an integrated circuit including the first circuit die. The method can additionally include providing a second circuit die of the integrated circuit, wherein the second circuit die has a second metal stack and is configured for connection to at least one of a package substrate or an additional die. The method can also include connecting the first metal stack to the second metal stack. Various other methods, systems, and computer-readable media are also disclosed.