Abstract: A signal processing system comprises an analogue shift register of the charge coupled type (24) fed from a sampling device (22) and controlled by a clock arrangement (26) having three independent clocks (26A, 26B and 26C). Clock (26A) determines the sampling rate of sampling device (22) and the rate at which such samples are clocked into register (24). Clock 26C determines the rate at which stored samples are clocked out of the register (24). Clocks 26A and 26C operate in the MHz range. Clock 26B operates in the KHz range and dictates the sample storage interval and clocks the stored samples through a number of storage sites in register (24) during the storage interval to reduce the adverse effects of geometrical and other inhomogeneities of the individual register sites on the individual stored samples.