Abstract: The present invention facilitates memory devices and operation thereof by employing a repair cache system 600 to correct or repair identified faulty memory locations. The repair cache system 600 includes a decoder that selects local repair location addresses from repair sets 610 according to a repair region address 604. Comparators 616 compare the selected local repair location addresses with a local repair address 606 to identify a match. Repair register banks 622 that comprise a plurality of repair registers are selected if an associated comparator 606 identifies a match. Then, a register within the associated register bank is selected according the repair region address 604 for read/write access. If a match is not identified, a memory location from a main memory 630 is selected for read/write access.

Abstract: Systems and methods fatigue a ferroelectric memory device. Within a single cycle, a group of selected ferroelectric memory cells is fatigued by reading a first logical value from the cells while also writing a second logical value to the memory cells. The first logical value is temporarily stored into latches of sense amplifiers associated with the selected memory cells in order to decipher logical values. Subsequently, the first logical value is written back to the ferroelectric memory cells and a cycle of the fatigue operation is ended.

Abstract: A memory circuit and method for reducing gate oxide stress is disclosed. The circuit includes a memory cell for storing data. The memory cell has a first 106 and a second 110 control terminal and a pass transistor 102. The pass transistor has a control gate coupled to the first control terminal. The memory circuit includes a drive circuit 900 having an output terminal 912 coupled to the second control terminal. The drive circuit is arranged to produce a control signal PL having a rise time and a fall time, wherein the fall time is greater than the rise time.

Abstract: A memory such as a FeRAM implements accelerated fatigue operations that simultaneously change the storage state of large numbers of memory cells and can be rapidly repeated. In one embodiment, the FeRAM includes multiple segments with plate lines in each segment being isolated from plate lines in other segments. A first fatigue operation uses standard read/write decoding for word lines but simultaneously activates all segments. A second fatigue operation activates all segments and all plate lines and exercises one row of memory cells in each plate line group. A third fatigue operation is similar to the second but cycles through rows in the plate line groups so that a number of repetitions of the third fatigue operation equally fatigue every FeRAM cell.

Abstract: A memory such as a FeRAM implements accelerated fatigue operations that simultaneously change the storage state of large numbers of memory cells and can be rapidly repeated. In one embodiment, the FeRAM includes multiple segments with plate lines in each segment being isolated from plate lines in other segments. A first fatigue operation uses standard read/write decoding for word lines but simultaneously activates all segments. A second fatigue operation activates all segments and all plate lines and exercises one row of memory cells in each plate line group. A third fatigue operation is similar to the second but cycles through rows in the plate line groups so that a number of repetitions of the third fatigue operation equally fatigue every FeRAM cell.

Abstract: A method and circuit for measuring a charge distribution for readout from FeRAM cells is fast enough for an on-chip defect detection and parameter adjustment. A comparator-type sense amplifier and a reference voltage generator measure a bit line charge or voltage using one readout of charge from an FeRAM cell and comparisons of the resulting bit line voltage to a series of reference voltages. A series of result signals from the sense amplifier indicates when the bit line voltage is approximately equal to the reference voltage. The results signals can be output for analysis and/or used internally for defect detection or setting of operating parameters such as a reference used during read operations.