Patents by Inventor John Yakura

John Yakura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4535721
    Abstract: A process for making stacked high voltage rectifiers includes initially doping a plurality of silicon wafers with paint-on dopants applied with an applicator that is gradually moved from the center to the outer edge of each wafer while the wafer is peripherally supported and rotated sufficiently slowly to prevent spin-off and runover of each dopant onto the reverse side of the wafer. The dopants are driven in by heating in a diffusion furnace. The same slow rotation and moving applicator technique then is used to coat only the N-doped side of the wafer with a paint-on noble metal dopant. The noble metal is driven in using a diffusion furnace at a temperature that is selected in accordance with the measured reverse recovery time of the wafer prior to noble metal diffusion.The wafers are silver coated and stacked, and a compression jig is used to exert compressive force on the stack while it is heated in a alloying furnace to a temperature sufficiently high to cause "wetting" of the silver.
    Type: Grant
    Filed: March 16, 1984
    Date of Patent: August 20, 1985
    Assignee: California Linear Circuits, Inc.
    Inventor: John Yakura
  • Patent number: 4510672
    Abstract: A process for making stacked high voltage rectifiers includes initially doping a plurality of silicon wafers with paint-on dopants applied with an applicator that is gradually moved from the center to the outer edge of each wafer while the wafer is peripherally supported and rotated sufficiently slowly to prevent spin-off and runover of each dopant onto the reverse side of the wafer. The dopants are driven in by heating in a diffusion furnace. The same slow rotation and moving applicator technique then is used to coat only the N-doped side of the wafer with a paint-on noble metal dopant. The noble metal is driven in using a diffusion furnace at a temperature that is selected in accordance with the measured reverse recovery time of the wafer prior to noble metal diffusion.The wafers are silver coated and stacked, and a compression jig is used to exert compressive force on the stack while it is heated in a alloying furnace to a temperature sufficiently high to cause "wetting" of the silver.
    Type: Grant
    Filed: September 23, 1982
    Date of Patent: April 16, 1985
    Assignee: California Linear Circuits, Inc.
    Inventor: John Yakura
  • Patent number: 4490111
    Abstract: A process for making stacked high voltage rectifiers includes initially doping a plurality of silicon wafers with paint-on dopants applied with an applicator that is gradually moved from the center to the outer edge of each wafer while the wafer is peripherally supported and rotated sufficiently slowly to prevent spin-off and runover of each dopant onto the reverse side of the wafer. The dopants are driven in by heating in a diffusion furnace. The same slow rotation and moving applicator technique then is used to coat only the N-doped side of the wafer with a paint-on noble metal dopant. The noble metal is driven in using a diffusion furnace at a temperature that is selected in accordance with the measured reverse recovery time of the wafer prior to noble metal diffusion.The wafers are silver coated and stacked, and a compression jig is used to exert compressive force on the stack while it is heated in an alloying furnace to a temperature sufficiently high to cause "wetting" of the silver.
    Type: Grant
    Filed: December 1, 1983
    Date of Patent: December 25, 1984
    Assignee: California Linear Circuits, Inc.
    Inventor: John Yakura