Abstract: A method of forming a low loss crystal quality waveguide is provided. The method includes providing a substrate and forming a dielectric layer on the substrate. A channel is formed by etching a portion of the dielectric layer. A selective growth of a Si Ge, or SiGe layer is performed in the area that defines the channel. Furthermore, the method includes thermally annealing the waveguide at a defined temperature range.

Abstract: A photodiode is formed in a recessed germanium (Ge) region in a silicon (Si) substrate. The Ge region may be fabricated by etching a hole through a passivation layer on the Si substrate and into the Si substrate and then growing Ge in the hole by a selective epitaxial process. The Ge appears to grow better selectively in the hole than on a Si or oxide surface. The Ge may grow up some or all of the passivation sidewall of the hole to conformally fill the hole and produce a recessed Ge region that is approximately flush with the surface of the substrate, without characteristic slanted sides of a mesa. The hole may be etched deep enough so the photodiode is thick enough to obtain good coupling efficiencies to vertical, free-space light entering the photodiode.

Abstract: A photodiode is formed in a recessed germanium (Ge) region in a silicon (Si) substrate. The Ge region may be fabricated by etching a hole through a passivation layer on the Si substrate and into the Si substrate and then growing Ge in the hole by a selective epitaxial process. The Ge appears to grow better selectively in the hole than on a Si or oxide surface. The Ge may grow up some or all of the passivation sidewall of the hole to conformally fill the hole and produce a recessed Ge region that is approximately flush with the surface of the substrate, without characteristic slanted sides of a mesa. The hole may be etched deep enough so the photodiode is thick enough to obtain good coupling efficiencies to vertical, free-space light entering the photodiode.

Abstract: A light conversion apparatus has a germanium-based photodiode, and a polysilicon-based receiving electrode for receiving light to be converted by the photodiode. The receiving electrode is coupled with the photodiode and permits the received light to substantially pass through it to the photodiode. The photodiode is capable of converting the received light into an electrical signal.

Abstract: A method of forming a low loss crystal quality waveguide is provided. The method includes providing a substrate and forming a dielectric layer on the substrate. A channel is formed by etching a portion of the dielectric layer. A selective growth of a Si Ge, or SiGe layer is performed in the area that defines the channel. Furthermore, the method includes thermally annealing the waveguide at a defined temperature range.

Abstract: A flip-bonding technique is used to fabricate complex micro-electromechanical systems. Various micromachined structures are fabricated on the front side of each of two wafers. One of the wafers is flipped over and bonded to the other wafer so that the front sides of the two wafers are bonded together in a flip-stacked configuration.

Abstract: An intermediate electrode layer is used to fabricate an integrated micro-electromechanical system. An intermediate electrode layer is formed on an integrated circuit wafer. The intermediate electrode layer places drive electrodes a predetermined height above the surface of the integrated circuit wafer. A micro-electromechanical system wafer having micromachined optical mirrors is bonded to the integrated circuit wafer such that the drive electrodes are positioned a predetermined distance from the optical mirrors.

Abstract: A coupler for coupling light in an optical system is described. Multiple discrete layers of alternating optical materials have respective first and second indexes of refraction. The thickness of each layer is a fraction of the light wavelength.

Abstract: A light conversion apparatus has a germanium-based photodiode, and a polysilicon-based receiving electrode for receiving light to be converted by the photodiode. The receiving electrode is coupled with the photodiode and permits the received light to substantially pass through it to the photodiode. The photodiode is capable of converting the received light into an electrical signal.

Abstract: A flip-bonding technique is used to fabricate complex micro-electromechanical systems. Various micromachined structures are fabricated on the front side of each of two wafers. One of the wafers is flipped over and bonded to the other wafer so that the front sides of the two wafers are bonded together in a flip-stacked configuration.

Abstract: A dummy handling substrate is used to form complex micro-electromechanical systems. A two-sided micromachined structure is fabricated by forming micromachined structures on a front side of a wafer, bonding the front side of the wafer to a dummy handling substrate, and forming micromachined structures on a back side of the wafer using the dummy handling substrate to handle the wafer during this back side processing. A second wafer containing micromachined features may be bonded to the back side of the first wafer using the dummy handling substrate to handle the first wafer during this bonding. The dummy handling substrate is removed from the front side of the wafer after back side processing and/or bonding of the second wafer.

Abstract: An intermediate electrode layer is used to fabricate an integrated micro-electromechanical system. An intermediate electrode layer is formed on an integrated circuit wafer. The intermediate electrode layer places drive electrodes a predetermined height above the surface of the integrated circuit wafer. A micro-electromechanical system wafer having micromachined optical mirrors is bonded to the integrated circuit wafer such that the drive electrodes are positioned a predetermined distance from the optical mirrors.

Abstract: An integrated-circuit (IC) chip formed with a capacitor comprising a lower layer of polysilicon clad with a thin film of TiSi.sub.2 serving as the lower plate of the capacitor, a layer of dielectric, a thin film of titanium nitride (TiN) on the upper surface of the dielectric to serve as the upper plate of the capacitor, a second layer of polysilicon (doped with phosphorous) over the TiN film, and metallization to make contact with the top plate of the capacitor.

Abstract: An integrated circuit device including a link point for electrically connecting a plurality of metal layers, comprising a first metal layer, a link insulating layer and a second metal layer. Diffusion barrier may be employed between the link insulator layer and each of the first metal layer and the second metal layer. The metal layers are connected by exposing the link point to a low-power laser for a relatively long pulse width.

Abstract: In a semiconductor device fabrication process, the SILO (Sealed Interface Local Oxidation) field oxide formation process is used to provide essentially vertical sidewalls between the field oxide surface and active regions. After field oxide formation and doping of active regions, the device is conformally coated with an oxide layer, which is patterned by a conventional photomasking process to define contact holes. Contact holes are then anisotropically etched through the oxide layer to the active regions. Conformal coating of the vertical sidewalls insures that an oxide sidewall spacer remains where the contact holes intersect the field oxide. Finally, a metal contact layer is deposited in the contact holes. The sidewall spacer automatically spaces the metal contact from the edges of the active region, thereby preventing leakage to the substrate.

Abstract: A method and apparatus for reliably forming low resistance links between two aluminum conductors deposited on an insulating polysilicon or amorphous silicon layer, employ a laser to bridge a lateral gap between the conductors. The apparatus and method are ideally suited for implementing defect avoidance using redundancy in large random access memories and in complex VLSI circuits. Only a single level of metal is employed and leads to both higher density and lower capacitance in comparison to prior techniques. Resistances in the range of one to ten ohms can be achieved for gap widths of approximately two to three microns.

Abstract: An integrated circuit device including a link point for electrically connecting a plurality of metal layers, comprising a first metal layer, a link insulating layer, a second metal layer and diffusion barrier layers between the link insulator layer and each of the first metal layer and the second metal layer. The metal layers are connected by exposing the link point to a low-power laser for a relatively long pulse width.

Abstract: An improved metal dual insulator semiconductor capacitor memory is disclosed. The memory contains a plurality of capacitor cells, each cell comprising a semiconductor substrate layer and a high conductivity layer sandwiching two insulator layers. The substrate is doped to provide avalanche breakdown in a surface depletion layer at a voltage comparable to the write voltage in the accumulation direction. The invention also provides a method of reading stored information without disturbing adjacent cells. A small variable voltage is applied across a "flat-band" portion of the hysteresis loop describing the voltage-capacitance relationship for the capacitor memory. A change or the absence of a change in the current through the capacitor indicates the state of the capacitor cell. Methods to fabricate the memory are also disclosed.

Abstract: An improved metal dual insulator semiconductor capacitor memory is disclosed. The memory contains a plurality of capacitor cells, each cell comprising a semiconductor substrate layer and a high conductivity layer sandwiching two insulator layers. The substrate is doped to provide avalanche breakdown in a surface depletion layer at a voltage comparable to the write voltage in the accumulation direction. The invention also provides a method of reading stored information without disturbing adjacent cells. A small variable voltage is applied across a "flat-band" portion of the hysteresis loop describing the voltage-capacitance relationship for the capacitor memory. A change or the absence of a change in the current through the capacitor indicates the state of the capacitor cell. Methods to fabricate the memory are also disclosed.

Abstract: An improved method for reading metal dual insulator semiconductor capacitor memories is disclosed. The memory contains a plurality of capacitor cells, each cell comprising a semiconductor substrate layer and a high conductivity layer sandwiching two insulator layers. The substrate is doped to provide avalanche breakdown in a surface depletion layer at a voltage comparable to the write voltage in the accumulation direction. According to the invention, a small variable voltage is applied across a selected cell or cells. The range of voltage includes a "flat-band" portion of the hysteresis loop describing the voltage-capacitance relationship for the capacitor memory. The unselected cells are maintained in a depletion state in which their capacitance is a minimum. A change or the absence of a change in the current through the capacitor indicates the state of the capacitor cell.