Abstract: A method of simulating communication channel noise comprising generating, by a FPGA or ASIC, a stream of uniformly distributed random variables using a cryptographic algorithm, applying a mathematical transform to the uniformly distributed random variables using the FPGA or ASIC to create a signal comprised of normally distributed random variables, adjusting a mean and variance of the signal using the FPGA or ASIC, outputting, by the FPGA or ASIC, an output noise signal, adding, by the FPGA or ASIC, I and Q samples of the output noise signal to I and Q symbols of a data carrier signal at complex baseband, modulating, using a modulator, the summed I and Q symbols to create a composite carrier signal, and upconverting using an upconverter, the composite carrier signal for transmission across a telecommunications channel to simulate a noisy telecommunications channel.

Abstract: A logarithmic (LOG) based adaptive algorithm to track RF power received at a receiver is provided. The method includes: receiving, by a variable gain amplifier (VGA) having exponential gain characteristics, an input signal; and providing log-based gain control of the input signal by determining a power of the input signal, and generating, according to the determined power, a voltage control signal using a log-based function, wherein the VGA amplifies the input signal based on the voltage control signal.

Abstract: Hyperchain information management techniques are provided for use in applications such as on-demand business collaboration. In accordance with such techniques, a hyperchain annotation methodology is provided. Such an annotation methodology enables interaction between loosely-coupled business processes or interacting partners and business entities. Annotated information components and process components for collaboration may be expressed as links. Further, techniques for realizing an on-demand message exchange, embedded status/state information, flexible collaborative business message exchange patterns, and a collaborative directory are provided.

Abstract: Techniques are provided for product life cycle management over an information network. More particularly, techniques are provided for decision support activation and management in accordance with a product life cycle management process such as a collaborative design process. In one aspect of the invention, a technique for managing at least one collaborative process performed in accordance with a first entity and at least a second entity, comprises the following steps/operations. Information associated with the at least one collaborative process is obtained. Based on at least a portion of the obtained information, an information structure (e.g., a context pyramid) representative of the collaborative process is dynamically maintained so as to assist at least one of the first entity and the second entity in managing at least a portion of the collaborative process.

Abstract: Resource allocation techniques are provided for use in managing escalation of on-demand business processes. For example, in one aspect of the invention, a technique for managing escalation of a business process comprises the following steps/operations. A request is obtained from a business process, the business process having one or more tasks associated therewith. The one or more tasks are mapped to one or more roles. One or more available resources are allocated for the one or more roles. At least one communication session is launched such that data associated with the business process may be transferred to the one or more allocated resources.

Abstract: A method and apparatus for detecting valid placement of library cells on chip images or hierarchy design images may be accomplished by determining a periodic pattern of the chip image, or hierarchical image. Once the repetitive pattern is recognized, this pattern is represented by a binary vector. Similarly, a binary vector is created for a particular cell library that is to be placed on the chip image or hierarchical design image. When the placement algorithm places the library cell on the chip or hierarchical image, the binary vector of the library cell is folded over a folded binary vector of the chip image or hierarchical design image to produce a component delta set. In essence, the component delta set indicates spacing violations between the library cell and the chip or hierarchical design image. When such a spacing violation is recognized, the placement algorithm can immediately reposition the library cell.

Abstract: A method for resizing the macro cells' boundaries of an integrated chip is disclosed and that becomes effectual after the initial floorplanning process has been completed. The method of the present invention apportions any excess area that is freed-up after the initial floorplanning process by altering the sizes or dimensions of the macro cell within the hierarchy of the integrated circuit in such a manner that the fractional change in the percentage occupancy is substantially constant among all macro cells at all hierarchy levels.