Patents by Inventor John Z. Colt, Jr.

John Z. Colt, Jr. has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10228685
    Abstract: A computer-implemented method, system, and/or computer program product controls manufacturing devices in a manufacturing environment. One or more processors receive sensor readings, which detect conditions that are unique to different areas within the manufacturing environment, in order to generate models of operations for each area in the manufacturing environment. One or more processors generate an ensemble model by extracting information from the models to describe a relationship between the conditions. One or more processors generate a device control signal, based on the ensemble model, that adjusts operations in the different areas in order to ameliorate the detected conditions.
    Type: Grant
    Filed: October 22, 2015
    Date of Patent: March 12, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: John Z. Colt, Jr., Venkata N. Pavuluri
  • Publication number: 20170115658
    Abstract: A computer-implemented method, system, and/or computer program product controls manufacturing devices in a manufacturing environment. One or more processors receive sensor readings, which detect conditions that are unique to different areas within the manufacturing environment, in order to generate models of operations for each area in the manufacturing environment. One or more processors generate an ensemble model by extracting information from the models to describe a relationship between the conditions. One or more processors generate a device control signal, based on the ensemble model, that adjusts operations in the different areas in order to ameliorate the detected conditions.
    Type: Application
    Filed: October 22, 2015
    Publication date: April 27, 2017
    Inventors: John Z. Colt, JR., Venkata N. Pavuluri
  • Patent number: 9397203
    Abstract: Device structures, fabrication methods, and design structures for a bipolar junction transistor. A first terminal of the bipolar junction transistor is formed from a section of a device layer of a semiconductor-on-insulator wafer. An intrinsic base of the bipolar junction transistor is formed from an epitaxially-grown section of a first semiconductor layer, which is coextensive with a sidewall of the section of the device layer. A second terminal of the bipolar junction transistor is formed from a second semiconductor layer that is coextensive with the epitaxially-grown section of the first semiconductor layer. The epitaxially-grown section of a first semiconductor layer defines a first junction with the section of the device layer, and the second semiconductor layer defines a second junction with the epitaxially-grown section of the first semiconductor layer.
    Type: Grant
    Filed: April 2, 2015
    Date of Patent: July 19, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: John Z. Colt, Jr., John J. Ellis-Monaghan, Leah M. Pastel, Steven M. Shank
  • Publication number: 20150214346
    Abstract: Device structures, fabrication methods, and design structures for a bipolar junction transistor. A first terminal of the bipolar junction transistor is formed from a section of a device layer of a semiconductor-on-insulator wafer. An intrinsic base of the bipolar junction transistor is formed from an epitaxially-grown section of a first semiconductor layer, which is coextensive with a sidewall of the section of the device layer. A second terminal of the bipolar junction transistor is formed from a second semiconductor layer that is coextensive with the epitaxially-grown section of the first semiconductor layer. The epitaxially-grown section of a first semiconductor layer defines a first junction with the section of the device layer, and the second semiconductor layer defines a second junction with the epitaxially-grown section of the first semiconductor layer.
    Type: Application
    Filed: April 2, 2015
    Publication date: July 30, 2015
    Inventors: John Z. Colt, JR., John J. Ellis-Monaghan, Leah M. Pastel, Steven M. Shank
  • Patent number: 9059230
    Abstract: Device structures, fabrication methods, and design structures for a bipolar junction transistor. A first terminal of the bipolar junction transistor is formed from a section of a device layer of a semiconductor-on-insulator wafer. An intrinsic base of the bipolar junction transistor is formed from an epitaxially-grown section of a first semiconductor layer, which is coextensive with a sidewall of the section of the device layer. A second terminal of the bipolar junction transistor is formed from a second semiconductor layer that is coextensive with the epitaxially-grown section of the first semiconductor layer. The epitaxially-grown section of a first semiconductor layer defines a first junction with the section of the device layer, and the second semiconductor layer defines a second junction with the epitaxially-grown section of the first semiconductor layer.
    Type: Grant
    Filed: January 10, 2014
    Date of Patent: June 16, 2015
    Assignee: International Business Machines Corporation
    Inventors: John Z. Colt, Jr., John J. Ellis-Monaghan, Leah M. Pastel, Steven M. Shank
  • Patent number: 7007855
    Abstract: A semiconductor wafer including a plurality of pits in the semiconductor wafer. The pits are arranged in an information-providing pattern and are readable after completion of processing on the wafer.
    Type: Grant
    Filed: March 17, 2000
    Date of Patent: March 7, 2006
    Assignee: International Business Machines Corporation
    Inventors: Brian C. Barker, Raymond J. Bunkofske, John Z. Colt, Jr., Perry G. Hartswick, John W. Lewis, Nancy T. Pascoe
  • Patent number: 6678569
    Abstract: A method and structure for controlling a manufacturing tool includes measuring different manufacturing parameters of the tool, transforming a plurality of time series of the manufacturing parameters into intermediate variables based on restrictions and historical reference statistics, generating a surrogate variable based on the intermediate variables, if the surrogate variable exceeds a predetermined limit, identifying a first intermediate variable, of the intermediate variables, that caused the surrogate variable to exceed the predetermined limit and identifying a first manufacturing parameter associated with the first intermediate variable, and inhibiting further operation of the tool until the first manufacturing parameter has been modified to bring the surrogate value within the predetermined limit.
    Type: Grant
    Filed: November 6, 2001
    Date of Patent: January 13, 2004
    Assignee: International Business Machines Corporation
    Inventors: Raymond J. Bunkofske, John Z. Colt, Jr., James J McGill, Nancy T. Pascoe, Maheswaran Surendra, Marc A. Taubenblatt, Asif Ghias
  • Patent number: 6584368
    Abstract: A method and structure for controlling a manufacturing tool includes measuring different manufacturing parameters of the tool, transforming a plurality of time series of the manufacturing parameters into intermediate variables based on restrictions and historical reference statistics, generating a surrogate variable based on the intermediate variables, if the surrogate variable exceeds a predetermined limit, identifying a first intermediate variable, of the intermediate variables, that caused the surrogate variable to exceed the predetermined limit and identifying a first manufacturing parameter associated with the first intermediate variable, and inhibiting further operation of the tool until the first manufacturing parameter has been modified to bring the surrogate value within the predetermined limit.
    Type: Grant
    Filed: September 17, 2002
    Date of Patent: June 24, 2003
    Assignee: International Business Machines Corporation
    Inventors: Raymond J. Bunkofske, John Z. Colt, Jr., James J. McGill, Nancy T. Pascoe, Maheswaran Surendra, Marc A. Taubenblatt, Asif Ghias
  • Patent number: 6442445
    Abstract: A method and structure for controlling a manufacturing tool includes measuring different manufacturing parameters of the tool, transforming a plurality of time series of the manufacturing parameters into intermediate variables based on restrictions and historical reference statistics, generating a surrogate variable based on the intermediate variables, if the surrogate variable exceeds a predetermined limit, identifying a first intermediate variable, of the intermediate variables, that caused the surrogate variable to exceed the predetermined limit and identifying a first manufacturing parameter associated with the first intermediate variable, and inhibiting further operation of the tool until the first manufacturing parameter has been modified to bring the surrogate value within the predetermined limit.
    Type: Grant
    Filed: March 19, 1999
    Date of Patent: August 27, 2002
    Assignee: International Business Machines Corporation,
    Inventors: Raymond J. Bunkofske, John Z. Colt, Jr., James J. McGill, Nancy T. Pascoe, Maheswaran Surendra, Marc A. Taubenblatt, Asif Ghias
  • Patent number: 6383892
    Abstract: An integrated circuit chip wherein one or more semiconductor devices are completely isolated from bulk effects of other semiconductor devices in the same circuit and a method of making the integrated circuit chip. The devices may be passive devices such as resistors, or active devices such as diodes, bipolar transistors or field effect transistors (FETs). A multi-layer semiconductor body is formed of, preferably silicon and silicon dioxide. A conducting region or channel is formed in one or more of the layers. For the FET, silicon above and below the channel region provides controllable gates with vertically symmetrical device characteristics. Buried insulator layers may be added to isolate the lower gate of individual devices from each other and to create multiple vertically stacked isolated devices. Both PFET and NFET devices can be made with independent doping profiles in both depletion and accumulation modes.
    Type: Grant
    Filed: January 5, 1999
    Date of Patent: May 7, 2002
    Assignee: International Business Machines Corporation
    Inventor: John Z. Colt, Jr.
  • Patent number: 6013936
    Abstract: An integrated circuit chip wherein one or more semiconductor devices are completely isolated from bulk effects of other semiconductor devices in the same circuit and a method of making the integrated circuit chip. The devices may be passive devices such as resistors, or active devices such as diodes, bipolar transistors or field effect transistors (FETs). A multi-layer semiconductor body is formed of, preferably silicon and silicon dioxide. A conducting region or channel is formed in one or more of the layers. For the FET, silicon above and below the channel region provides controllable gates with vertically symmetrical device characteristics. Buried insulator layers may be added to isolate the lower gate of individual devices from each other and to create multiple vertically stacked isolated devices. Both PFET and NFET devices can be made with independent doping profiles in both depletion and accumulation modes.
    Type: Grant
    Filed: August 6, 1998
    Date of Patent: January 11, 2000
    Assignee: International Business Machines Corporation
    Inventor: John Z. Colt, Jr.