Abstract: A method and a system for wafer level burn-in testing of a circuit featuring a flip-jumper to permit selectively connecting signals to the interconnect sites on the wafer that are in constant electrical communication with the circuit.

Abstract: A module and method for interconnecting integrated circuits. The module includes an insulative body that features conductive traces having differing resistivities associated therewith. To that end, the insulative body has, disposed therein, a conductive bond pad and a plurality of spaced apart conductive traces, one of which is in electrical communication with the bond pad, with each of the plurality of conductive traces are formed from a material having a resistivity associated therewith. The resistivity of the material from which one of the plurality of conductive traces is formed being greater than the resistivity of the material from which the remaining conductive traces are formed and defines a decoupling capacitor therebetween.

Abstract: A VLSI chip tester for defining and performing functional tests, delay tests, and DC parametric tests on VLSI chips. The VLSI chip under test is mounted to a paddle card which, in turn, is detachably held under pressure against a circuit board mounted in a test fixture. A connector is sandwiched between the paddle card and circuit board. The connector has insulated, spaced-apart conductors that are orthogonal to the paddle card and circuit board, and that provide electrical contact between each pin of the VLSI chip under test and a corresponding pad on the circuit board. Shift register circuits mounted to the circuit board provide a single stage corresponding to each I/O pin of the device under test. Each stage may function as an input or output device. A computer or computers are coupled to the shift register circuits through appropriate cabling and driver/receiver/termination circuits. Test data to be sent to or from the computer may be shifted serially into or out of the shift register circuits.

Abstract: A system and method for calibrating scanning beam systems, such as electron beam systems, so that a plurality of such systems are compatible one with another, thereby allowing an object that is scanned on one system to be transferred to another system while still maintaining proper alignment between the pattern(s) scanned on the object by one system and the pattern(s) scanned on the object by another system. A calibration plate, having an array of calibration marks thereon at prescribed locations, is made on a first system. This plate is then transferred to a second system where the location of the calibration marks is measured. The measured locations are fitted mathematically to the prescribed locations in order to minimize error. Nonetheless, some error will be present due to the slight misalignments and nonlinearities, such as mirror distortion, that are present between any two scanning beam systems. This error is determined by comparing the fitted measured locations to the prescribed locations.