Patents by Inventor John Zijun Shen
John Zijun Shen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8316378Abstract: A method includes receiving data in a first data processing module, and enabling a second data processing module when at least one signal time slot of the received data comprises data that complies with a first data transmission standard. The method also includes exchanging signals between the first data processing module and software executing in a processor, and determining that a software configuration of the second data processing module has been completed. The method also includes processing the data in the second data processing module for the at least one signal time slot, and enabling a third data processing module upon a completion of processing at least one data block in the second data processing module, and determining that a software configuration of the third data processing module has been completed, the at least one data block comprising multiple signal time slots.Type: GrantFiled: October 20, 2008Date of Patent: November 20, 2012Assignee: MediaTek Inc.Inventors: John Zijun Shen, Carsten Aagaard Pedersen, Deepak Mathew, Paul Donald Krivacek, Aiguo Yan, Timothy Perrin Fisher-Jeffes
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Patent number: 8054922Abstract: A system includes a receiver for receiving a modulated signal. The receiver includes a gain estimator for converting complex data representative of constellation points of the modulated signal into scalar data representation. The gain estimator is configured to fold a first portion of the scalar data representation onto a second portion of the scalar data representation. The gain estimator is further configured to estimate a constellation gain value from the folded first portion and the second portion of the scalar data representation.Type: GrantFiled: August 11, 2008Date of Patent: November 8, 2011Assignee: MediaTek Inc.Inventors: Carsten Aagaard Pedersen, John Zijun Shen, Aiguo Yan, Deepak Mathew, Marko Kocic, Timothy Perrin Fisher-Jeffes, Thomas Keller
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Patent number: 7953958Abstract: A joint detection system is configured to perform joint detection of received signals and includes a joint detection accelerator and a host processor. The joint detection accelerator may include a memory unit to store input data values, intermediate results and output data values; one or more computation units to process the input data values and the intermediate results, and to provide output data values to the memory unit; a controller to control the memory and the one or more computation units to perform joint detection processing; and an external interface to receive the input data values from the host processor and to provide output data values to the host processor. The computation units may include a complex multiply accumulate unit, a simplified complex multiply accumulate unit and a normalized floating point divider. The memory unit may include an input memory, a matrix memory, a main memory and an output memory.Type: GrantFiled: June 12, 2007Date of Patent: May 31, 2011Assignee: MediaTek Inc.Inventors: John Zijun Shen, Paul D. Krivacek, Thomas J. Barber, Jr., Lidwine Martinot, Aiguo Yan, Marko Kocic
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Patent number: 7949925Abstract: A joint detection system and associated methods are provided. A joint detection system is configured to perform joint detection of received signals. The joint detection system includes a joint detector accelerator configured to perform an operation of the joint detection of the received signals, wherein the joint detection includes computing joint detection variables. The operation includes a multiply and accumulate operation resulting in a value in an accumulator, and the value in the accumulator includes a plurality of bits. The joint detector accelerator is configured to select a subset of bits of the plurality of bits of the value in the accumulator, where the subset of bits selected is configurable. The joint detector accelerator is further configured to store the subset of bits into a memory as a fixed point representation.Type: GrantFiled: October 11, 2006Date of Patent: May 24, 2011Assignee: MediaTek Inc.Inventors: Lidwine Martinot, Aiguo Yan, Marko Kocic, Thomas J. Barber, Jr., John Zijun Shen
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Patent number: 7924948Abstract: A joint detection system and associated methods are provided. The joint detection system is configured to perform joint detection of received signals. The joint detection system includes a programmable digital signal processor (DSP) configured to generate initial channel estimates corresponding to propagation channels, wherein each of the initial channel estimates includes a plurality of values. The programmable DSP is further configured to determine one or more pre-scaling factors for one or more of the initial channel estimates. The pre-scaling factors are at least partially based on at least one of the plurality of values of one or more of the initial channel estimates. The programmable DSP is further configured to pre-scale the initial channel estimates by the pre-scaling factors.Type: GrantFiled: October 11, 2006Date of Patent: April 12, 2011Assignee: MediaTek Inc.Inventors: Marko Kocic, Aiguo Yan, Lidwine Martinot, Thomas J. Barber, Jr., John Zijun Shen
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Patent number: 7916841Abstract: A joint detection system and associated methods are provided. The joint detection system is configured to perform joint detection of received signals and includes a joint detector accelerator and a programmable digital signal processor (DSP). The joint detector accelerator is configured to perform front-end processing of first data inputted to the joint detector accelerator and output second data resulting from the front-end processing. The joint detector accelerator is further configured to perform back-end processing using at least third data inputted to the joint detector accelerator. The programmable DSP is coupled to the joint detector accelerator, and the programmable DSP is programmed to perform at least one intermediate processing operation using the second data outputted by the joint detector accelerator. The programmable DSP is further programmed to output the third data resulting from the intermediate processing operation to the joint detector accelerator.Type: GrantFiled: October 11, 2006Date of Patent: March 29, 2011Assignee: MediaTek Inc.Inventors: Aiguo Yan, Lidwine Martinot, Marko Kocic, Paul D. Krivacek, Thomas J. Barber, Jr., John Zijun Shen
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Publication number: 20090165019Abstract: A method includes receiving data in a first data processing module, and enabling a second data processing module when at least one signal time slot of the received data comprises data that complies with a first data transmission standard. The method also includes exchanging signals between the first data processing module and software executing in a processor, and determining that a software configuration of the second data processing module has been completed. The method also includes processing the data in the second data processing module for the at least one signal time slot, and enabling a third data processing module upon a completion of processing at least one data block in the second data processing module, and determining that a software configuration of the third data processing module has been completed, the at least one data block comprising multiple signal time slots.Type: ApplicationFiled: October 20, 2008Publication date: June 25, 2009Applicant: MediaTek Inc.Inventors: John Zijun Shen, Carsten Aagaard Pedersen, Deepak Mathew, Paul Donald Krivacek, Aiguo Yan, Timothy Perrin Fisher-Jeffes
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Publication number: 20090161745Abstract: A system includes a receiver for receiving a modulated signal. The receiver includes a gain estimator for converting complex data representative of constellation points of the modulated signal into scalar data representation. The gain estimator is configured to fold a first portion of the scalar data representation onto a second portion of the scalar data representation. The gain estimator is further configured to estimate a constellation gain value from the folded first portion and the second portion of the scalar data representation.Type: ApplicationFiled: August 11, 2008Publication date: June 25, 2009Inventors: Carsten Aagaard Pedersen, John Zijun Shen, Aiguo Yan, Deepak Mathew, Marko Kocic, Timothy Perrin Fisher-Jeffes, Thomas Keller
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Publication number: 20080089448Abstract: A joint detection system and associated methods are provided. A joint detection system is configured to perform joint detection of received signals. The joint detection system includes a joint detector accelerator configured to perform an operation of the joint detection of the received signals, wherein the joint detection includes computing joint detection variables. The operation includes a multiply and accumulate operation resulting in a value in an accumulator, and the value in the accumulator includes a plurality of bits. The joint detector accelerator is configured to select a subset of bits of the plurality of bits of the value in the accumulator, where the subset of bits selected is configurable. The joint detector accelerator is further configured to store the subset of bits into a memory as a fixed point representation.Type: ApplicationFiled: October 11, 2006Publication date: April 17, 2008Applicant: Analog Devices, Inc.Inventors: Lidwine Martinot, Aiguo Yan, Marko Kocic, Thomas J. Barber, John Zijun Shen
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Publication number: 20080080468Abstract: A joint detection system is configured to perform joint detection of received signals and includes ajoint detection accelerator and a host processor. The joint detection accelerator may include a memory unit to store input data values, intermediate results and output data values; one or more computation units to process the input data values and the intermediate results, and to provide output data values to the memory unit; a controller to control the memory and the one or more computation units to perform joint detection processing; and an external interface to receive the input data values from the host processor and to provide output data values to the host processor. The computation units may include a complex multiply accumulate unit, a simplified complex multiply accumulate unit and a normalized floating point divider. The memory unit may include an input memory, a matrix memory, a main memory and an output memory.Type: ApplicationFiled: June 12, 2007Publication date: April 3, 2008Applicant: Analog Devices, Inc.Inventors: John Zijun Shen, Paul D. Krivacek, Thomas J. Barber, Lidwine Martinot, Aiguo Yan, Marko Kocic
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Publication number: 20080080638Abstract: A joint detection system and associated methods are provided. The joint detection system is configured to perform joint detection of received signals and includes a joint detector accelerator and a programmable digital signal processor (DSP). The joint detector accelerator is configured to perform front-end processing of first data inputted to the joint detector accelerator and output second data resulting from the front-end processing. The joint detector accelerator is further configured to perform back-end processing using at least third data inputted to the joint detector accelerator. The programmable DSP is coupled to the joint detector accelerator, and the programmable DSP is programmed to perform at least one intermediate processing operation using the second data outputted by the joint detector accelerator. The programmable DSP is further programmed to output the third data resulting from the intermediate processing operation to the joint detector accelerator.Type: ApplicationFiled: October 11, 2006Publication date: April 3, 2008Applicant: Analog Devices, Inc.Inventors: Aiguo Yan, Lidwine Martinot, Marko Kocic, Paul D. Krivacek, Thomas J. Barber, John Zijun Shen
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Publication number: 20080080645Abstract: A joint detection system and associated methods are provided. The joint detection system is configured to perform joint detection of received signals. The joint detection system includes a programmable digital signal processor (DSP) configured to generate initial channel estimates corresponding to propagation channels, wherein each of the initial channel estimates includes a plurality of values. The programmable DSP is further configured to determine one or more pre-scaling factors for one or more of the initial channel estimates. The pre-scaling factors are at least partially based on at least one of the plurality of values of one or more of the initial channel estimates. The programmable DSP is further configured to pre-scale the initial channel estimates by the pre-scaling factors.Type: ApplicationFiled: October 11, 2006Publication date: April 3, 2008Applicant: Analog Devices, Inc.Inventors: Marko Kocic, Aiguo Yan, Lidwine Martinot, Thomas J. Barber, John Zijun Shen