Abstract: Embodiments of a method and/or an apparatus to test a delay lock loop circuit, chipset, or memory controller or memory controller hub (MCH) are described.

Abstract: In general, in one aspect, the disclosure describes an apparatus for calibrating signals. The apparatus includes a receiver pair to receive a differential signal and a reference signal and to generate at least one comparison signal reflecting where a first signal of the differential signal and a second signal of the differential signal cross each other with respect to the reference signal. The second signal is a negative compliment of the first signal. The apparatus further includes a phase detector to determine a phase error based on the at least one comparison signal. The apparatus also includes an edge delay control driver pair to adjust the differential signal based on the phase error.

Abstract: A write pointer (21) from a write pointer circuit (13) may cause a demultiplexer circuit (12) to direct data from a memory cell (11A–11N) to a desired bit location (0–4) in a register 14. A read pointer (20) may cause a multiplexer circuit (15) to select data from a desired bit location in the register to provide as output data (19) or to select one of the bits of the write pointer. The write pointer may be incremented by a data strobe signal (17). The state of the write pointer may be determined by reading the bits of the write pointer, and the write pointer may be synchronized via a reset line (18).

Abstract: A device and method for calibrating a slew rate is disclosed. The slew rate may be for a driver of a bi-directional buffer. A driver outputs a signal having a frequency. A receiver is coupled to the driver. A frequency counter measures the frequency of the signal. A calibrated slew rate is determined by the frequency of a waveform of the signal. Different waveforms may be determined for the pull-up and pull-down calibrations.

Abstract: According to one embodiment of the present invention, a circuit is disclosed. The circuit includes a plurality of driver slices, a portion of the plurality of the driver slices being used to provide a target impedance; a digital matching logic to select the portion of the plurality of the driver slices; and an analog matching circuit to produce a bias voltage to match pull-up and pull-down.

Abstract: Embodiments of the invention include a memory controller to interface to memory. In one embodiment, the memory controller includes a pull-up calibration terminal to couple to an external pull-up resistor, a pull-down calibration terminal to couple to an external pull-down resistor, a voltage reference node, a first switch coupled between the pull-up calibration terminal and the voltage reference node, and a second switch coupled between the pull-down calibration terminal and the voltage reference node. The first switch and the second switch may be selectively closed to generate an internal voltage reference on the voltage reference node in a normal mode that may be used for comparison with an input signal to receive data.