Patents by Inventor Johnatan Kantarovsky

Johnatan Kantarovsky has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250040221
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a high-electron-mobility transistor and methods of manufacture. The structure includes: a gate structure; a first field plate on a first side of the gate structure; and a second field plate on a second side of the gate structure, independent from the first field plate.
    Type: Application
    Filed: July 27, 2023
    Publication date: January 30, 2025
    Inventors: Johnatan A. KANTAROVSKY, Mark D. LEVY, Alvin J. JOSEPH, Santosh SHARMA, Michael J. ZIERAK
  • Patent number: 12183814
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to multi-channel transistors and methods of manufacture. The structure includes: a gate structure; a single channel layer in a channel region under the gate structure; a drift region adjacent to the gate structure; and multiple channel layers in the drift region coupled to the single channel layer under the gate structure.
    Type: Grant
    Filed: March 25, 2024
    Date of Patent: December 31, 2024
    Assignee: GLOBALFOUNDRIES U.S. Inc.
    Inventors: Steven J. Bentley, Francois Hebert, Lawrence Selvaraj Susai, Johnatan A Kantarovsky, Michael Zierak, Mark D. Levy, John Ellis-Monaghan
  • Patent number: 12159910
    Abstract: Structures with an isolation region and fabrication methods for a structure having an isolation region. The structure includes a semiconductor substrate, a first isolation region surrounding a portion of the semiconductor substrate, a device in the portion of the semiconductor substrate, and a second isolation region surrounding the first isolation region and the portion of the semiconductor substrate.
    Type: Grant
    Filed: February 15, 2022
    Date of Patent: December 3, 2024
    Assignee: GlobalFoundries U.S. Inc.
    Inventors: Uppili Raghunathan, Vibhor Jain, Sebastian Ventrone, Johnatan Kantarovsky, Yves Ngu
  • Patent number: 12119383
    Abstract: Disclosed are a transistor and a method for forming the transistor. The method includes concurrently forming gate and source/drain openings through an uppermost layer (i.e., a dielectric layer) in a stack of layers. The method can further include: depositing and patterning gate conductor material so that a first gate section is in the gate opening and a second gate section is above the gate opening and so that the source/drain openings are exposed; extending the depth of the source/drain openings; and depositing and patterning source/drain conductor material so that a first source/drain section is in each source/drain opening and a second source/drain section is above each source/drain opening. Alternatively, the method can include: forming a plug in the gate opening and sidewall spacers in the source/drain openings; extending the depth of source/drain openings; depositing and patterning the source/drain conductor material; and subsequently depositing and patterning the gate conductor material.
    Type: Grant
    Filed: February 24, 2023
    Date of Patent: October 15, 2024
    Assignee: GlobalFoundries U.S. Inc.
    Inventors: Johnatan A. Kantarovsky, Mark D. Levy, Jeonghyun Hwang, Siva P. Adusumilli, Ajay Raman
  • Publication number: 20240250157
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to heater terminal contacts, methods of operation and methods of manufacture. The structure includes: a heterojunction bipolar transistor having a collector, sub-collector region, emitter and base region; and heater terminal contacts electrically coupled to the sub-collector region.
    Type: Application
    Filed: January 20, 2023
    Publication date: July 25, 2024
    Inventors: Uppili S. RAGHUNATHAN, Vibhor JAIN, Yves T. NGU, Johnatan A. KANTAROVSKY, Sebastian T. VENTRONE
  • Publication number: 20240249992
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to heater elements, methods of operation and methods of manufacture. The structure includes: an active device; a heater element under the active device and within a semiconductor substrate; and a contact to the heater element and the active device.
    Type: Application
    Filed: January 20, 2023
    Publication date: July 25, 2024
    Inventors: Uppili S. RAGHUNATHAN, Vibhor JAIN, Yves T. NGU, Johnatan A. KANTAROVSKY, Sebastian T. VENTRONE
  • Patent number: 12046633
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to airgap structures in a doped region under one or more transistors and methods of manufacture. The structure includes: a semiconductor material comprising a doped region; one or more sealed airgap structures breaking up the doped region of the semiconductor material; and a field effect transistor over the one or more sealed airgap structures and the semiconductor material.
    Type: Grant
    Filed: January 25, 2021
    Date of Patent: July 23, 2024
    Assignee: GLOBALFOUNDRIES U.S. Inc.
    Inventors: Mark D. Levy, Siva P. Adusumilli, Johnatan A. Kantarovsky, Vibhor Jain
  • Publication number: 20240178310
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a high-electron-mobility transistor and methods of manufacture. The structure includes: a gate structure; and a channel region under the gate structure, the channel region having a first portion including a first thickness and a second portion having a second thickness greater than the first thickness, the second portion being positioned remotely from the gate structure.
    Type: Application
    Filed: November 29, 2022
    Publication date: May 30, 2024
    Inventors: Santosh SHARMA, Rajendran KRISHNASAMY, Johnatan A. KANTAROVSKY
  • Publication number: 20240145469
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a depletion mode device with a programmable element used for chip programming and circuit configuration and methods of manufacture and operation. In particular, the structure includes a programmable element on an active layer of semiconductor material, and a depletion mode device comprising a dual gate connected to the programmable element.
    Type: Application
    Filed: October 26, 2022
    Publication date: May 2, 2024
    Inventors: Santosh SHARMA, Johnatan A. KANTAROVSKY
  • Publication number: 20240128328
    Abstract: The present disclosure relates to a structure which includes at least one gate structure over semiconductor material, the at least one gate structure comprising an active layer, a gate metal extending from the active layer and a sidewall spacer on sidewalls of the gate metal, and a field plate aligned with the at least one gate structure and isolated from the gate metal by the sidewall spacer.
    Type: Application
    Filed: October 12, 2022
    Publication date: April 18, 2024
    Inventors: Michael J. ZIERAK, Steven J. BENTLEY, Santosh SHARMA, Mark D. LEVY, Johnatan A. KANTAROVSKY
  • Publication number: 20240105595
    Abstract: Embodiments of the disclosure provide an electrically programmable fuse (efuse) over crystalline semiconductor material. A structure according to the disclosure includes a plurality of crystalline semiconductor layers. Each crystalline semiconductor layer includes a compound material. A metallic layer is on the plurality of crystalline semiconductor layers. The metallic layer has a lower resistivity than an uppermost layer of the plurality of crystalline semiconductor layers. A pair of gate conductors is on respective portions of the metallic layer. The metallic layer defines an electrically programmable fuse (efuse) link between the gate conductors.
    Type: Application
    Filed: September 22, 2022
    Publication date: March 28, 2024
    Inventors: Johnatan A. Kantarovsky, Santosh Sharma, Michael J. Zierak, Steven J. Bentley, Ephrem G. Gebreselasie
  • Publication number: 20240088242
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to high-electron-mobility transistors and methods of manufacture. A structure includes: a semiconductor layer on a semiconductor material; a gate structure on the semiconductor layer; a drain region comprising the semiconductor layer and which is adjacent to the gate structure; an ohmic contact which includes at least one terminal connection connecting to the semiconductor material, the ohmic contact being adjacent to the drain region and spaced away from the gate structure; and a capacitance reducing structure adjacent to the drain region.
    Type: Application
    Filed: September 13, 2022
    Publication date: March 14, 2024
    Inventors: Johnatan A. KANTAROVSKY, Rebouh BENELBAR, Ajay RAMAN, Michel J. ABOU-KHALIL, Rajendran KRISHNASAMY, Randy L. WOLF
  • Patent number: 11916119
    Abstract: Disclosed are embodiments of a transistor (e.g., a III-V high electron mobility transistor (HEMT), a III-V metal-insulator-semiconductor HEMT (MISHEMT), or the like) that has multiple self-aligned terminals. The self-aligned terminals include a self-aligned gate, a self-aligned source terminal and, optionally, a self-aligned drain terminal. By forming self-aligned terminals during processing, the separation distances between the terminals (e.g., between the gate and source terminal and, optionally, between the gate and drain terminal) can be reduced in order to reduce device size and to improve performance (e.g., to reduce on resistance and increase switching speeds). Also disclosed herein are method embodiments for forming such a transistor.
    Type: Grant
    Filed: November 3, 2021
    Date of Patent: February 27, 2024
    Assignee: GlobalFoundries U.S. Inc.
    Inventors: Zhong-Xiang He, Jeonghyun Hwang, Ramsey M. Hazbun, Brett T. Cucci, Ajay Raman, Johnatan A. Kantarovsky
  • Patent number: 11901304
    Abstract: The disclosure provides an integrated circuit (IC) structure with fluorescent materials, and related methods. An IC structure according to the disclosure may include a layer of fluorescent material on an IC component. The layer of fluorescent material defines a portion of an identification marker for the IC structure.
    Type: Grant
    Filed: May 18, 2021
    Date of Patent: February 13, 2024
    Assignee: GlobalFoundries U.S. Inc.
    Inventors: Sunil K. Singh, Vibhor Jain, Siva P. Adusumilli, Sebastian T. Ventrone, Johnatan A. Kantarovsky, Yves T. Ngu
  • Patent number: 11881506
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to gate structures and methods of manufacture. The structure includes: a gate structure comprising a horizontal portion and a substantially vertical stem portion; and an air gap surrounding the substantially vertical stem portion and having a curved surface under the horizontal portion.
    Type: Grant
    Filed: July 27, 2021
    Date of Patent: January 23, 2024
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: Johnatan A. Kantarovsky, Mark D. Levy, Brett T. Cucci, Jeonghyun Hwang, Siva P. Adusumilli
  • Publication number: 20230317627
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to devices with airgap structures and methods of manufacture. The structure includes: a semiconductor substrate with a trap-rich region; one or more airgap structures within the semiconductor substrate; at least one deep trench isolation structure laterally surrounding the one or more airgap structures and extending into the semiconductor substrate; and a device over the one or more airgap structures.
    Type: Application
    Filed: March 29, 2022
    Publication date: October 5, 2023
    Inventors: Uppili S. RAGHUNATHAN, Vibhor JAIN, Siva P. ADUSUMILLI, Yves T. NGU, Johnatan A. KANTAROVSKY, Sebastian T. VENTRONE
  • Patent number: 11764258
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to airgap isolation structures and methods of manufacture. The structure includes: a bulk substrate material; a first airgap isolation structure in the bulk substrate material and having a first aspect ratio; and a second airgap isolation structure in the bulk substrate material and having a second aspect ratio different from the first aspect ratio.
    Type: Grant
    Filed: December 1, 2020
    Date of Patent: September 19, 2023
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: Brett T. Cucci, Siva P. Adusumilli, Johnatan A. Kantarovsky, Claire E. Kardos, Sen Liu
  • Patent number: 11749717
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a transistor with an embedded isolation layer in a bulk substrate and methods of manufacture. The structure includes: a bulk substrate; an isolation layer embedded within the bulk substrate and below a top surface of the bulk substrate; a deep trench isolation structure extending through the bulk substrate and contacting the embedded isolation layer; and a gate structure over the top surface of the bulk substrate and vertically spaced away from the embedded isolation layer, the deep trench isolation structure and the embedded isolation layer defining an active area of the gate structure in the bulk substrate.
    Type: Grant
    Filed: May 6, 2022
    Date of Patent: September 5, 2023
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: Uzma Rana, Anthony K. Stamper, Johnatan A. Kantarovsky, Steven M. Shank, Siva P. Adusumilli
  • Publication number: 20230261062
    Abstract: Structures with an isolation region and fabrication methods for a structure having an isolation region. The structure includes a semiconductor substrate, a first isolation region surrounding a portion of the semiconductor substrate, a device in the portion of the semiconductor substrate, and a second isolation region surrounding the first isolation region and the portion of the semiconductor substrate.
    Type: Application
    Filed: February 15, 2022
    Publication date: August 17, 2023
    Inventors: Uppili Raghunathan, Vibhor Jain, Sebastian Ventrone, Johnatan Kantarovsky, Yves Ngu
  • Patent number: 11710655
    Abstract: Embodiments of the disclosure provide an integrated circuit (IC) structure, including a semiconductor-based isolation structure on a substrate. A shallow trench isolation (STI) structure may be positioned on the semiconductor-based isolation structure. An active semiconductor region is on the substrate and adjacent each of the semiconductor-based isolation structure and the STI structure. The active semiconductor region includes a doped semiconductor material. At least one device on the active semiconductor region may be horizontally distal to the STI structure.
    Type: Grant
    Filed: October 20, 2021
    Date of Patent: July 25, 2023
    Assignee: GlobalFoundries U.S. Inc.
    Inventors: Anthony K. Stamper, Henry L. Aldridge, Jr., Johnatan A. Kantarovsky, Jeonghyun Hwang