Abstract: A memory cell may comprise a field-effect transistor structure comprising a gate structure, the gate structure comprising a floating gate electrode separated from a channel of field-effect transistor structure by a gate isolation; a spontaneously polarizable memory layer, wherein the spontaneously polarizable memory layer covers completely an upper surface of the floating gate electrode and wherein the spontaneously polarizable memory layer covers one or more lateral surfaces of the floating gate electrode; a gate electrode, wherein the spontaneously polarizable memory layer is disposed between the floating gate electrode and the gate electrode to form a capacitive memory structure; and a lever electrode, wherein the spontaneously polarizable memory layer is disposed between the floating gate electrode and the lever electrode to form a lever structure.