Abstract: A method and apparatus for modifying data synchronization of an application responsive to the frequency of application usage are disclosed. Data describing a frequency with which the application is used is captured by a portable computing device. For example, data describing timestamps when the application receives input or data describing a timestamp when the application was the primary application being executed are captured. It is determined whether the frequency of interaction with which the application is used equals or exceeds a threshold value. For example, the portable computing device determines whether the application has received an input or was the primary application within a predetermined time interval from the current time. Responsive to determining the frequency of interaction with the application does not equal or exceed the threshold value, data synchronization for the application is disabled. In one embodiment, the portable computing device stops data synchronization for the application.

Abstract: A system is implemented on a mobile communication device for establishing preferred contacts for a central user of the mobile communication device. The system comprises a data collection device that captures the central user's interaction with other users on a network according to frequency during situational factors; and a query apparatus that inquires, for current situational factors, which contacts are preferred that the central user will communicate with based on central user's past interactions during same situational factors that correspond only to the central user. A list is provided to the central user of one or more of the preferred contacts that the central user selects from; and an application launcher is communicatively coupled to the list for display of the list of preferred contacts that are also functionally related to the application launcher.

Abstract: A variable sector size for a flash memory device is disclosed. The total available memory of the flash memory device is divided into sub-units. Each sub-unit has a pre-decoder coupled with it to enable operations on the memory within that sub-unit. A sector size control register is coupled with pre-decoder enabling logic which is coupled with the pre-decoders. The sector size control register and pre-decoder enabling logic determines how many pre-decoders, and therefore how many sub-units, are activated at a given time for a given memory operation.

Abstract: An input circuit for a flash memory device is disclosed. The input circuit includes an input for receiving a voltage signal from an external source representing a digital logic signal. The input circuit further includes a pull up circuit which is coupled with the input and pulls the input to a high logic level when the input is not connected to any external source.

Abstract: The reduction of electrical noise in a high voltage distribution path of a high density flash memory device is disclosed. High voltage brought on-chip from an external power source is transmitted over separate isolated voltage distribution paths to a voltage generator circuit. The voltage generator pumps up the voltage of one of the voltage paths and uses the pumped up voltage to control the distribution of the voltage from the other voltage path, whereby electrical noise from the voltage pump is isolated from the distributed voltage.

Abstract: A system for optimizing the equalization pulse of a read sense amplifier is disclosed. A number of capacitor circuits are provided that can be coupled to a timing circuit in a variety of combinations. The different combinations of coupled and decoupled capacitor circuits result in different durational lengths of the equalization pulse. A testing sequence determines the optimal durational length of the equalization pulse by testing the different combinations of coupled capacitors. The optimal combination is then permanently stored in attribute cells for optimizing the equalization pulse in normal operation.

Abstract: A low supply voltage negative charge pump for generating a relatively high negative voltage to control gates of selected memory cells via wordlines in an array of flash EEPROM memory cells during flash erasure includes charge pump means (210) formed of a plurality of charge pump stages (201-206) and coupling capacitor means (C201-C212) for delivering clock signals to the plurality of charge pump stages. Each of the plurality of charge pump stages is formed of an N-channel intrinsic pass transistor (N1-N6), an N-channel intrinsic initialization transistor (MD1-MD6), and an N-channel intrinsic precharge transistor (MX3-MX7, MX1) which are disposed in separate p-wells so as to reduce body effect. As a result, the negative charge pump is operable using a supply voltage of +3 volts or lower.

Abstract: A flash memory device is divided into two or more banks. Each bank includes a number of sectors. Each sector includes flash memory cells. Each bank has a decoder that selectively receives an address from an input address buffer or from an internal address sequencer controlled by an internal state machine. The output data for each bank can be communicated to a read sense amplifier or a verify sense amplifier. The read sense amplifier connects to the output buffer while the verify sense amplifier connects to the state machine. When one bank receives a write command, the internal state machine takes control and starts the program or erase operation. While one bank is busy with a program or erase operation, the other bank can be accessed for a read operation. Power is supplied for each of the read and write operations via an internal multiplexed multi power supply source that provides an amount of power needed based on the memory operation being performed.

Abstract: A non-volatile memory that allows simultaneous reading and writing operations by time multiplexing a single x-decode path between read and write operations. This is accomplished using appropriate timing signals to store/latch a first word line for a first operation and then relinquishing the x-decode path so that a second operation can load an address and access a second word line.

Abstract: A voltage booster circuit includes a driver circuit (117) for generating a 3-state output for driving wordlines via row decoder circuits in an array of flash EEPROM memory cells during read and programming modes of operation. The driver circuit effectively disconnects a large booster capacitor (115) in order to allow a small charge pump (114) to further pump up the wordline voltage during programming. As a result, the booster pump has improved efficiency since there is achieved a significant reduction in power consumption.

Abstract: A reference circuit for overerase correction in a flash memory includes a reference flash memory cell biased in a substantially similar manner to that of an overerased flash memory cell. The leakage current for the reference flash memory cell is preset to a tolerable level of leakage current for a maximum operating temperature of the flash memory and the reference flash memory cell tracks the temperature characteristics of the overerased flash memory cell, to avoid costly overcorrection at high temperatures.

Abstract: A low supply voltage negative charge pump for generating a relatively high negative voltage to control gates of selected memory cells via wordlines in an array of flash EEPROM memory cells during flash erasure includes charge pump means (210) formed of a plurality of charge pump stages (201-206) and coupling capacitor means (C201-C212) for delivering clock signals to the plurality of charge pump stages. Each of the plurality of charge pump stages is formed of an N-channel intrinsic pass transistor (N1-N6), an N-channel intrinsic initialization transistor (MD1-MD6), and an N-channel intrinsic precharge transistor (MX3-MX7, MX1) which are disposed in separate p-wells so as to reduce body effect. As a result, the negative charge pump is operable using a supply voltage of +3 volts or lower.

Abstract: A distributed negative gate power supply for generating and selectively supplying a relatively high negative voltage to control gates of memory cells in selected half-sectors via wordlines in an array of flash EEPROM memory cells during flash erasure. The distributed negative gate power supply includes a main charge pumping circuit (20a, 20b), a plurality of distribution sector pumping means (18a-18p). Each of the plurality of distribution sector pumping circuits is responsive to a half-sector select signal for selectively connecting the primary negative voltage to the wordlines of the selected half-sectors.

Abstract: A thin film magnetic head is fabricated with shaping magnetic thin films, preferably formed of Permalloy, which have a stepped configuration. The thin films are deposited between the insulation layer surrounding the electrical coil and below the second pole layer P2 to form a double yoke. The thin films have corners at the stepped areas which pin the domain sites so that the magnetization of the P2 layer is properly aligned, thereby improving the data signal that is being recorded.

Abstract: An improved over-erased bit correction structure is provided for performing a correction operation on over-erased memory cells in an array of flash EEPROM memory cells after erase operation so as to render high endurance. Sensing circuitry (20) is used to detect column leakage current indicative of an over-erased bit during an APDE mode of operation and for generating a logic signal representative of data stored in the memory cell. A data input buffer circuit (26) is used to compare the logic signal and a data signal representative of data programmed in the memory cell so as to generate a bit match signal. A pulse counter (30) is coupled to the data input buffer circuit for counting a plurality of programming pulses applied thereto.

Abstract: An improved redundancy architecture is provided for an array of flash EEPROM cells which permit repair of defective columns of memory cells in the array with redundant columns of memory cells on a sector-by-sector basis. The redundancy circuitry includes a plurality of sector-based redundancy blocks (2-8) each having redundant columns of memory cells extending through the plurality of sectors. Sector selection transistors (Q1,Q2) are provided for dividing the redundant columns into different segments, each residing in at least one of the plurality of sectors and for isolating the different segments so as to allow independent use from other segments in the same redundant column in repairing defective columns in the corresponding ones of the plurality of sectors.

Abstract: A thin-film magnetoresistive playback head having films providing magnetic shielding and magnetic bias. At least one of the magnetic shield layers is also conductive so that the functions of shielding and biasing are combined. Preferably, both shield layers are conductive. A multiple element channel head is disclosed in which the magnetic/conductive layers extend in series from one transducer section to the next, allowing a single bias current to bias all of the sections.

Abstract: A thin-film magnetoresistive playback head having films providing magnetic shielding and magnetic bias. At least one of the magnetic shield layers is also conductive so that the functions of shielding and biasing are combined. Preferably, both shield layers are conductive. A multiple element channel head is disclosed in which the magnetic/conductive layers extend in series from one transducer section to the next, allowing a single bias current to bias all of the sections.

Abstract: A positive power supply for generating and supplying a regulated positive potential to control gates of selected memory cells via word lines in an array of flash EEPROM memory cells during programming includes a clock circuit (18b) for generating a pair of non-overlapping clock signals and charge pump means (18c) responsive to an external power supply potential (VCC) and to the non-overlapping clock signals for generating a high positive voltage. A regulator circuit (20) responsive to the high positive voltage and a reference voltage is provided for controlling the regulated positive potential so that it is independent of the external power supply potential (VCC).

Abstract: A negative power supply for generating and supplying a regulated negative potential to control gates of selected memory cells via wordlines in an array of flash EEPROM memory cells during flash erasure includes charge pumping means (12) formed of a plurality of charge pump stages (401-404) for generating a high negative voltage, and cancellation means coupled to each stage of the charge pump means for effectively canceling out threshold voltage drops in the charge pump means. A regulator means (16) responsive to the high negative voltage and a reference potential is provided for generating the regulated negative potential so that it is independent of an external supply potential (VCC).