Abstract: In accordance with the objectives of the invention a new methodology is provided that assures that integrated process results are verified and assured prior to the installation of processing tools as part of modifying or updating of a semiconductor manufacturing foundry. The complete semiconductor manufacturing complement of processing tools is sub-divided into short-loops or sub-modules, which are then combined into a full loop. This combination of sub-modules into modules that closer approach a full complement of processing tools can be accomplished in a gradual manner, whereby one or more sub-loops are first combined and evaluated, to this combination one or more additional sub-groups may be added whereby each of these latter sub-groups may also have been created by combining one or more (original) sub-loops. This process is continued to the point where a full complement of process equipment has been created, completing the full processing loops of the semiconductor manufacturing facility.

Abstract: In accordance with the objectives of the invention a new methodology is provided that assures that integrated process results are verified and assured prior to the installation of processing tools as part of modifying or updating of a semiconductor manufacturing foundry. The complete semiconductor manufacturing complement of processing tools is sub-divided into short-loops or sub-modules, which are then combined into a full loop. This combination of sub-modules into modules that closer approach a full complement of processing tools can be accomplished in a gradual manner, whereby one or more sub-loops are first combined and evaluated, to this combination one or more additional sub-groups may be added whereby each of these latter sub-groups may also have been created by combining one or more (original) sub-loops. This process is continued to the point where a full complement of process equipment has been created, completing the full processing loops of the semiconductor manufacturing facility.

Abstract: A method for controlling and/or calibrating rapid thermal process systems is described. One or more wafers comprising a silicon semiconductor substrate having a refractory metal layer thereon are silicided in a RTP system at different temperatures. Sheet resistance uniformity of the wafer is measured thereby detecting silicidation phase transition temperature points at the highest uniformity points. The temperature points are used to calibrate or to reset the RTP system. A plurality of wafers comprising a silicon semiconductor substrate having a refractory metal layer thereon can be silicided in each of a plurality of rapid thermal process systems. Sheet resistance uniformity of each of the wafers is measured thereby detecting silicidation phase transition temperature points by highest sheet resistance uniformity for each of the RTP systems. The temperature points are used to match temperatures for each of the RTP systems.

Abstract: A method for controlling and/or calibrating rapid thermal process systems is described. One or more wafers comprising a silicon semiconductor substrate having a refractory metal layer thereon are silicided in a RTP system at different temperatures. Sheet resistance uniformity of the wafer is measured thereby detecting silicidation phase transition temperature points at the highest uniformity points. The temperature points are used to calibrate or to reset the RTP system. A plurality of wafers comprising a silicon semiconductor substrate having a refractory metal layer thereon can be silicided in each of a plurality of rapid thermal process systems. Sheet resistance uniformity of each of the wafers is measured thereby detecting silicidation phase transition temperature points by highest sheet resistance uniformity for each of the RTP systems. The temperature points are used to match temperatures for each of the RTP systems.