Abstract: Typically, primary electrical connection between a semiconductor chip and an external solder ball contact on a Ball Grid or Chip Scale Package is by way of a via extending through a dielectric substrate. The aspect ratio between via diameter and depth is critical for reliable and high yield solder ball attachment during printed circuit board assembly. Excellent ball adherence and reliability of BGA solder ball contacts is achieved through controlling the aspect ratio of the substrate vias by partially plating a solid solderable conductor core in each via. An improved via structure is disclosed wherein the depth of the viva is reduced without the negative effects of alternate methods, such as thinner substrates, or wider vias.

Abstract: Typically, primary electrical connection between a semiconductor chip and an external solder ball contact on a Ball Grid or Chip Scale Package is by way of a via extending through a dielectric substrate. The aspect ratio between via diameter and depth is critical for reliable and high yield solder ball attachment during printed circuit board assembly. Excellent ball adherence and reliability of BGA solder ball contacts is achieved through controlling the aspect ratio of the substrate vias by partially plating a solid solderable conductor core in each via. An improved via structure is disclosed wherein the depth of the viva is reduced without the negative effects of alternate methods, such as thinner substrates, or wider vias.

Abstract: Typically, primary electrical connection between a semiconductor chip and an external solder ball contact on a Ball Grid or Chip Scale Package is by way of a via extending through a dielectric substrate. The aspect ratio between via diameter and depth is critical for reliable and high yield solder ball attachment during printed circuit board assembly. Excellent ball adherence and reliability of BGA solder ball contacts is achieved through controlling the aspect ratio of the substrate vias by partially plating a solid solderable conductor core in each via. An improved via structure is disclosed wherein the depth of the via is reduced without the negative effects of alternate methods, such as thinner substrates, or wider vias.

Abstract: A semiconductor device comprising a lead frame that includes a large area mount pad having small elevated pads to which a semiconductor chip is attached. The small mount pads coupled with usage of a minimal amount of chip attach adhesive provide improved reliability against vapor phase package cracking, and further allow a given lead frame to be used by a family of chip sizes and shapes. The large pad provides good thermal dissipation, as well as stress relief during fabrication of the lead frame.

Abstract: Typically, primary electrical connection between a semiconductor chip and an external solder ball contact on a Ball Grid or Chip Scale Package is by way of a via extending through a dielectric substrate. The aspect ratio between via diameter and depth is critical for reliable and high yield solder ball attachment during printed circuit board assembly. Excellent ball adherence and reliability of BGA solder ball contacts is achieved through controlling the aspect ratio of the substrate vias by partially plating a solid solderable conductor core in each via. An improved via structure is disclosed wherein the depth of the via is reduced without the negative effects of alternate methods, such as thinner substrates, or wider vias.

Abstract: Typically, primary electrical connection between a semiconductor chip and an external solder ball contact on a Ball Grid or Chip Scale Package is by way of a via extending through a dielectric substrate. The aspect ratio between via diameter and depth is critical for reliable and high yield solder ball attachment during printed circuit board assembly. Excellent ball adherence and reliability of BGA solder ball contacts is achieved through controlling the aspect ratio of the substrate vias by partially plating a solid solderable conductor core in each via. An improved via structure is disclosed wherein the depth of the via is reduced without the negative effects of alternate methods, such as thinner substrates, or wider vias.

Abstract: Typically, primary electrical connection between a semiconductor chip and an external solder ball contact on a Ball Grid or Chip Scale Package is by way of a via extending through a dielectric substrate. The aspect ratio between via diameter and depth is critical for reliable and high yield solder bail attachment during printed circuit board assembly. Excellent ball adherence and reliability of BGA solder ball contacts is achieved through controlling the aspect ratio of the substrate vias by partially plating a solid solderable conductor core in each via. An improved via structure is disclosed wherein the depth of the via is reduced without the negative effects of alternate methods, such as thinner substrates, or wider vias.

Abstract: A system and method for packaging a semiconductor chip, the system comprising a semiconductor chip having a contact point, a top surface, and a bottom surface; a housing which encapsulates the top surface of the semiconductor chip wherein the bottom surface is unencapsulated; a pin having a top member encapsulated inside the housing and a protruding member extending outside the housing, the pin providing a conduit through which an electrical charge may travel; a bond wire electrically connected to the pin to the contact point on the semiconductor chip to provide an electrical path from the pin to the semiconductor chip; and a fixture having a matrix of cavities for receiving and supporting the protruding member of the pin during packaging. The system and method result in a packaged semiconductor device which is cost effective, results in smaller package dimensions, and reduces tooling lead-time and manufacturing costs.

Abstract: A semiconductor device comprising a lead frame that includes a large area mount pad having small elevated pads to which a semiconductor chip is attached. The small mount pads coupled with usage of a minimal amount of chip attach adhesive provide improved reliability against vapor phase package cracking, and further allow a given lead frame to be used by a family of chip sizes and shapes. The large pad provides good thermal dissipation, as well as stress relief during fabrication of the lead frame.

Abstract: The invention is a semiconductor package (10) and to the method of making in which the backside (23) of a semiconductor die (13) is mounted to one part of a package (11) with an adhesive (12) which may be both thermally and electrically conductive. The face (22) of the semiconductor die (13) is attached to a second part of the package (18) to direct heat away form the face (22) of the semiconductor die (13).

Abstract: A system (10) for coupling conductive pellets (40) to a component (12) of an integrated circuit has a substantially planar ribbon (14) that includes a conductive material. A punching apparatus (16) and (38) penetrates the ribbon (14) to form the conductive pellets (40). The punching apparatus (16) and (38) also moves relative to the component (12) to the conductive pellets (40) to the component (12).