Patents by Inventor Johnny Chew

Johnny Chew has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7250669
    Abstract: A first method of reducing semiconductor device substrate effects comprising the following steps. O+or O2+are selectively implanted into a silicon substrate to form a silicon-damaged silicon oxide region. One or more devices are formed over the silicon substrate proximate the silicon-damaged silicon oxide region within at least one upper dielectric layer. A passivation layer is formed over the at least one upper dielectric layer. The passivation layer and the at least one upper dielectric layer are patterned to form a trench exposing a portion of the silicon substrate over the silicon-damaged silicon oxide region. The silicon-damaged silicon oxide region is selectively etched to form a channel continuous and contiguous with the trench whereby the channel reduces the substrate effects of the one or more semiconductor devices.
    Type: Grant
    Filed: August 2, 2004
    Date of Patent: July 31, 2007
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Lap Chan, Sanford Chu, Chit Hwei Ng, Purakh Verma, Jia Zhen Zheng, Johnny Chew, Choon Beng Sia
  • Publication number: 20050167828
    Abstract: A method of fabricating an inductor using bonding techniques in the manufacture of integrated circuits is described. Bonding pads are provided over a semiconductor substrate. Input/output connections are made to at least two of the bonding pads. A plurality of wire bond loops are made between each two of the bonding pads wherein the plurality of wire bond loops forms the inductor.
    Type: Application
    Filed: March 31, 2005
    Publication date: August 4, 2005
    Inventors: Kiat Yeo, Hai Ian, Jiangud Ma, Manh Do, Johnny Chew
  • Patent number: 6869884
    Abstract: A first method of reducing semiconductor device substrate effects comprising the following steps. O+ or O2+ are selectively implanted into a silicon substrate to form a silicon-damaged silicon oxide region. One or more devices are formed over the silicon substrate proximate the silicon-damaged silicon oxide region within at least one upper dielectric layer. A passivation layer is formed over the at least one upper dielectric layer. The passivation layer and the at least one upper dielectric layer are patterned to form a trench exposing a portion of the silicon substrate over the silicon-damaged silicon oxide region. The silicon-damaged silicon oxide region is selectively etched to form a channel continuous and contiguous with the trench whereby the channel reduces the substrate effects of the one or more semiconductor devices.
    Type: Grant
    Filed: August 22, 2002
    Date of Patent: March 22, 2005
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Lap Chan, Sanford Chu, Chit Hwei Ng, Purakh Verma, Jia Zhen Zheng, Johnny Chew, Choon Beng Sia
  • Publication number: 20050009357
    Abstract: A first method of reducing semiconductor device substrate effects comprising the following steps. O+or O2+are selectively implanted into a silicon substrate to form a silicon-damaged silicon oxide region. One or more devices are formed over the silicon substrate proximate the silicon-damaged silicon oxide region within at least one upper dielectric layer. A passivation layer is formed over the at least one upper dielectric layer. The passivation layer and the at least one upper dielectric layer are patterned to form a trench exposing a portion of the silicon substrate over the silicon-damaged silicon oxide region. The silicon-damaged silicon oxide region is selectively etched to form a channel continuous and contiguous with the trench whereby the channel reduces the substrate effects of the one or more semiconductor devices.
    Type: Application
    Filed: August 2, 2004
    Publication date: January 13, 2005
    Inventors: Lap Chan, Sanford Chu, Chit Ng, Purakh Verma, Jia Zheng, Johnny Chew, Choon Sia
  • Publication number: 20040038542
    Abstract: A first method of reducing semiconductor device substrate effects comprising the following steps. O+ or O2+ are selectively implanted into a silicon substrate to form a silicon-damaged silicon oxide region. One or more devices are formed over the silicon substrate proximate the silicon-damaged silicon oxide region within at least one upper dielectric layer. A passivation layer is formed over the at least one upper dielectric layer. The passivation layer and the at least one upper dielectric layer are patterned to form a trench exposing a portion of the silicon substrate over the silicon-damaged silicon oxide region. The silicon-damaged silicon oxide region is selectively etched to form a channel continuous and contiguous with the trench whereby the channel reduces the substrate effects of the one or more semiconductor devices.
    Type: Application
    Filed: August 22, 2002
    Publication date: February 26, 2004
    Applicant: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Lap Chan, Sanford Chu, Chit Hwei Ng, Purakh Verma, Jia Zhen Zheng, Johnny Chew, Choon Beng Sia
  • Patent number: 6486017
    Abstract: A new method is provided for the creation of a horizontal spiral inductor over the surface of a silicon substrate. A first layer of dielectric is deposited over the surface of the substrate, this first layer of dielectric is patterned and etched creation islands of first dielectric material overlying the surface of the substrate, the islands of first dielectric material align with coils of a thereover to be created spiral inductor. The openings created in the layer of dielectric by the patterning and etching of the first layer of dielectric are filled by selective deposition of epitaxial silicon therein. Second and third layers of dielectric are successively deposited over the surface of the first layer of dielectric. A spiral horizontal inductor is then created over the surface of the third layer of dielectric.
    Type: Grant
    Filed: June 4, 2002
    Date of Patent: November 26, 2002
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Purakh Raj Verma, Sanford Chu, Johnny Chew, Sia Choon Beng