Patents by Inventor Johnny Chew
Johnny Chew has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7573081Abstract: A new method is provided for creating an inductor on the surface of a silicon substrate. The invention provides overlying layers of oxide fins beneath a metal inductor. The oxide fins provide the stability support for the overlying metal inductor while also allowing horizontal air columns to simultaneously exist underneath the inductor. Overlying layers of air cavities that are spatially inserted between the created overlying layers of oxide fins can be created under the invention by repetitive application of the mask used. The presence of the air wells on the surface of the substrate significantly reduces parasitic capacitances and series resistance of the inductor associated with the substrate.Type: GrantFiled: September 11, 2006Date of Patent: August 11, 2009Assignees: Chartered Semiconductor Manufacturing Ltd., National University of SingaporeInventors: Lap Chan, Kok Wai Johnny Chew, Cher Liang Cha, Chee Tee Chua
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Patent number: 7250669Abstract: A first method of reducing semiconductor device substrate effects comprising the following steps. O+or O2+are selectively implanted into a silicon substrate to form a silicon-damaged silicon oxide region. One or more devices are formed over the silicon substrate proximate the silicon-damaged silicon oxide region within at least one upper dielectric layer. A passivation layer is formed over the at least one upper dielectric layer. The passivation layer and the at least one upper dielectric layer are patterned to form a trench exposing a portion of the silicon substrate over the silicon-damaged silicon oxide region. The silicon-damaged silicon oxide region is selectively etched to form a channel continuous and contiguous with the trench whereby the channel reduces the substrate effects of the one or more semiconductor devices.Type: GrantFiled: August 2, 2004Date of Patent: July 31, 2007Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Lap Chan, Sanford Chu, Chit Hwei Ng, Purakh Verma, Jia Zhen Zheng, Johnny Chew, Choon Beng Sia
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Publication number: 20070007623Abstract: A new method is provided for creating an inductor on the surface of a silicon substrate. The invention provides overlying layers of oxide fins beneath a metal inductor. The oxide fins provide the stability support for the overlying metal inductor while also allowing horizontal air columns to simultaneously exist underneath the inductor. Overlying layers of air cavities that are spatially inserted between the created overlying layers of oxide fins can be created under the invention by repetitive application of the mask used. The presence of the air wells on the surface of the substrate significantly reduces parasitic capacitances and series resistance of the inductor associated with the substrate.Type: ApplicationFiled: September 11, 2006Publication date: January 11, 2007Inventors: Lap Chan, Kok Wai Johnny Chew, Cher Liang Cha, Chee Tee Chua
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Patent number: 7105420Abstract: A new method is provided for creating an inductor on the surface of a silicon substrate. The invention provides overlying layers of oxide fins beneath a metal inductor. The oxide fins provide the stability support for the overlying metal inductor while also allowing horizontal air columns to simultaneously exist underneath the inductor. Overlying layers of air cavities that are spatially inserted between the created overlying layers of oxide fins can be created under the invention by repetitive application of the mask used. The presence of the air wells on the surface of the substrate significantly reduces parasitic capacitances and series resistance of the inductor associated with the substrate.Type: GrantFiled: October 7, 1999Date of Patent: September 12, 2006Assignees: Chartered Semiconductor Manufacturing Ltd., National University of SingaporeInventors: Lap Chan, Kok Wai Johnny Chew, Cher Liang Cha, Chee Tee Chua
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Patent number: 7023315Abstract: A method of fabricating an inductor using bonding techniques in the manufacture of integrated circuits is described. Bonding pads are provided over a semiconductor substrate. Input/output connections are made to at least two of the bonding pads. A plurality of wire bond loops are made between each two of the bonding pads wherein the plurality of wire bond loops forms the inductor.Type: GrantFiled: May 29, 2003Date of Patent: April 4, 2006Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Kiat Seng Yeo, Hai Peng Tan, Jianguo Ma, Manh Anh Do, Kok Wai Johnny Chew
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Publication number: 20050167828Abstract: A method of fabricating an inductor using bonding techniques in the manufacture of integrated circuits is described. Bonding pads are provided over a semiconductor substrate. Input/output connections are made to at least two of the bonding pads. A plurality of wire bond loops are made between each two of the bonding pads wherein the plurality of wire bond loops forms the inductor.Type: ApplicationFiled: March 31, 2005Publication date: August 4, 2005Inventors: Kiat Yeo, Hai Ian, Jiangud Ma, Manh Do, Johnny Chew
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Patent number: 6869884Abstract: A first method of reducing semiconductor device substrate effects comprising the following steps. O+ or O2+ are selectively implanted into a silicon substrate to form a silicon-damaged silicon oxide region. One or more devices are formed over the silicon substrate proximate the silicon-damaged silicon oxide region within at least one upper dielectric layer. A passivation layer is formed over the at least one upper dielectric layer. The passivation layer and the at least one upper dielectric layer are patterned to form a trench exposing a portion of the silicon substrate over the silicon-damaged silicon oxide region. The silicon-damaged silicon oxide region is selectively etched to form a channel continuous and contiguous with the trench whereby the channel reduces the substrate effects of the one or more semiconductor devices.Type: GrantFiled: August 22, 2002Date of Patent: March 22, 2005Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Lap Chan, Sanford Chu, Chit Hwei Ng, Purakh Verma, Jia Zhen Zheng, Johnny Chew, Choon Beng Sia
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Publication number: 20050009357Abstract: A first method of reducing semiconductor device substrate effects comprising the following steps. O+or O2+are selectively implanted into a silicon substrate to form a silicon-damaged silicon oxide region. One or more devices are formed over the silicon substrate proximate the silicon-damaged silicon oxide region within at least one upper dielectric layer. A passivation layer is formed over the at least one upper dielectric layer. The passivation layer and the at least one upper dielectric layer are patterned to form a trench exposing a portion of the silicon substrate over the silicon-damaged silicon oxide region. The silicon-damaged silicon oxide region is selectively etched to form a channel continuous and contiguous with the trench whereby the channel reduces the substrate effects of the one or more semiconductor devices.Type: ApplicationFiled: August 2, 2004Publication date: January 13, 2005Inventors: Lap Chan, Sanford Chu, Chit Ng, Purakh Verma, Jia Zheng, Johnny Chew, Choon Sia
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Patent number: 6803848Abstract: A new structure and method is provided for the creation of an inductor on the surface of a silicon semiconductor substrate. The inductor is of a helix coil design having upper level and lower level conductors further having an axis whereby the axis of the helix coil of the inductor is parallel to the plane of the underlying substrate. Under the first embodiment of the invention, the height of the helix coil that is created on the surface of a silicon substrate is uniform. Under the second embodiment of the invention the height of the helix coil of the inductor of the invention is uniform while a ferromagnetic core is inserted between the upper and the lower level conductors of the helix coil. Under the third embodiment of the invention, the height of the helix coil that is created on the surface of a silicon substrate is non-uniform.Type: GrantFiled: October 15, 2002Date of Patent: October 12, 2004Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Kiat Seng Yeo, Hai Peng Tan, Jian Guo Ma, Manh Anh Do, Kok Wai Johnny Chew
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Patent number: 6800533Abstract: A new structure is provided for the creation of an inductor on the surface of a silicon semiconductor substrate. The inductor is of spiral design and perpendicular to the plane of the underlying substrate. Conductor line width can be selected as narrow or wide, ferromagnetic material can be used to fill the spaces between the conductors of the spiral inductor. The spiral inductor of the invention can further by used in series or in series with conventional horizontal inductors.Type: GrantFiled: March 6, 2000Date of Patent: October 5, 2004Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Kiat Seng Yeo, Hai Peng Tan, Jian Guo Ma, Manh Anh Do, Kok Wai Johnny Chew
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Publication number: 20040038542Abstract: A first method of reducing semiconductor device substrate effects comprising the following steps. O+ or O2+ are selectively implanted into a silicon substrate to form a silicon-damaged silicon oxide region. One or more devices are formed over the silicon substrate proximate the silicon-damaged silicon oxide region within at least one upper dielectric layer. A passivation layer is formed over the at least one upper dielectric layer. The passivation layer and the at least one upper dielectric layer are patterned to form a trench exposing a portion of the silicon substrate over the silicon-damaged silicon oxide region. The silicon-damaged silicon oxide region is selectively etched to form a channel continuous and contiguous with the trench whereby the channel reduces the substrate effects of the one or more semiconductor devices.Type: ApplicationFiled: August 22, 2002Publication date: February 26, 2004Applicant: Chartered Semiconductor Manufacturing Ltd.Inventors: Lap Chan, Sanford Chu, Chit Hwei Ng, Purakh Verma, Jia Zhen Zheng, Johnny Chew, Choon Beng Sia
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Publication number: 20030205778Abstract: A method of fabricating an inductor using bonding techniques in the manufacture of integrated circuits is described. Bonding pads are provided over a semiconductor substrate. Input/output connections are made to at least two of the bonding pads. A plurality of wire bond loops are made between each two of the bonding pads wherein the plurality of wire bond loops forms the inductor.Type: ApplicationFiled: May 29, 2003Publication date: November 6, 2003Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING LTD.Inventors: Kiat Seng Yeo, Hat Peng Tan, Jianguo Ma, Manh Anh Do, Kok Wai Johnny Chew
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Patent number: 6611188Abstract: A new structure is provided for the creation of an inductor on the surface of a silicon semiconductor substrate. The inductor is of spiral design and perpendicular to the plane of the underlying substrate. Conductor line width can be selected as narrow or wide, ferromagnetic material can be used to fill the spaces between the conductors of the spiral inductor. The spiral inductor of the invention can further by used in series or in series with conventional horizontal inductors.Type: GrantFiled: September 3, 2002Date of Patent: August 26, 2003Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Kiat Seng Yeo, Hai Yeng Tan, Jiang Guo Ma, Manh Anh Do, Kok Wai Johnny Chew
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Patent number: 6586309Abstract: A method of fabricating an inductor using bonding techniques in the manufacture of integrated circuits is described. Bonding pads are provided over a semiconductor substrate. Input/output connections are made to at least two of the bonding pads. A plurality of wire bond loops are made between each two of the bonding pads wherein the plurality of wire bond loops forms the inductor.Type: GrantFiled: April 24, 2000Date of Patent: July 1, 2003Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Kiat Seng Yeo, Hai Peng Tan, Jianguo Ma, Manh Anh Do, Kok Wai Johnny Chew
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Patent number: 6535098Abstract: A new structure and method is provided for the creation of an inductor on the surface of a silicon semiconductor substrate. The inductor is of a helix coil design having upper level and lower level conductors further having an axis whereby the axis of the helix coil of the inductor is parallel to the plane of the underlying substrate. Under the first embodiment of the invention, the height of the helix coil that is created on the surface of a silicon substrate is uniform. Under the second embodiment of the invention the height of the helix coil of the inductor of the invention is uniform while a ferromagnetic core is inserted between the upper and the lower level conductors of the helix coil. Under the third embodiment of the invention, the height of the helix coil that is created on the surface of a silicon substrate is non-uniform.Type: GrantFiled: March 6, 2000Date of Patent: March 18, 2003Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Kiat Seng Yeo, Hai Peng Tan, Jian Guo Ma, Manh Anh Do, Kok Wai Johnny Chew
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Publication number: 20030043010Abstract: A new structure and method is provided for the creation of an inductor on the surface of a silicon semiconductor substrate. The inductor is of a helix coil design having upper level and lower level conductors further having an axis whereby the axis of the helix coil of the inductor is parallel to the plane of the underlying substrate. Under the first embodiment of the invention, the height of the helix coil that is created on the surface of a silicon substrate is uniform. Under the second embodiment of the invention the height of the helix coil of the inductor of the invention is uniform while a ferromagnetic core is inserted between the upper and the lower level conductors of the helix coil. Under the third embodiment of the invention, the height of the helix coil that is created on the surface of a silicon substrate is non-uniform.Type: ApplicationFiled: October 15, 2002Publication date: March 6, 2003Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING LTD.Inventors: Kiat Seng Yeo, Hai Peng Tan, Jian Guo Ma, Manh Anh Do, Kok Wai Johnny Chew
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Publication number: 20030013264Abstract: A new structure is provided for the creation of an inductor on the surface of a silicon semiconductor substrate. The inductor is of spiral design and perpendicular to the plane of the underlying substrate. Conductor line width can be selected as narrow or wide, ferromagnetic material can be used to fill the spaces between the conductors of the spiral inductor. The spiral inductor of the invention can further by used in series or in series with conventional horizontal inductors.Type: ApplicationFiled: September 3, 2002Publication date: January 16, 2003Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING LTD.Inventors: Kiat Seng Yeo, Hai Peng Tan, Jian Guo Ma, Manh Anh Do, Kok Wai Johnny Chew
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Patent number: 6486017Abstract: A new method is provided for the creation of a horizontal spiral inductor over the surface of a silicon substrate. A first layer of dielectric is deposited over the surface of the substrate, this first layer of dielectric is patterned and etched creation islands of first dielectric material overlying the surface of the substrate, the islands of first dielectric material align with coils of a thereover to be created spiral inductor. The openings created in the layer of dielectric by the patterning and etching of the first layer of dielectric are filled by selective deposition of epitaxial silicon therein. Second and third layers of dielectric are successively deposited over the surface of the first layer of dielectric. A spiral horizontal inductor is then created over the surface of the third layer of dielectric.Type: GrantFiled: June 4, 2002Date of Patent: November 26, 2002Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Purakh Raj Verma, Sanford Chu, Johnny Chew, Sia Choon Beng
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Patent number: 6140197Abstract: A new method of fabricating an inductor utilizing air as an underlying barrier in the manufacture of integrated circuits is described. A metal line is provided overlying a dielectric layer on a semiconductor substrate. An intermetal dielectric layer is deposited overlying the metal line and the dielectric layer. The intermetal dielectric layer is patterned whereby a plurality of openings are made through the intermetal dielectric layer to the semiconductor substrate. Thereafter, an oxide layer is deposited overlying the intermetal dielectric layer and capping the plurality of openings thereby forming air gaps within the intermetal dielectric layer. A metal plug is formed through the oxide layer and the intermetal dielectric layer to the metal line.Type: GrantFiled: August 30, 1999Date of Patent: October 31, 2000Assignees: Chartered Semiconductor Manufacturing Ltd., National University of SingaporeInventors: Shau-Fu Sanford Chu, Kok Wai Johnny Chew, Chee Tee Chua, Cher Liang Cha