Abstract: A method for test pattern compression generates a first test pattern comprising a plurality of bits. The method identifies bits comprising a don't-care bit value in the first test pattern and replaces the identified bit values with random bit values, to generate a second test pattern. The method determines a fault coverage level of the second test pattern. In the event the determined fault coverage level of the second test pattern exceeds a predetermined individual test pattern fault coverage level, for at least one bit position in the second test pattern corresponding to a replaced identified bit value and detecting at least one fault, the method exchanges the don't care value in the bit position in the first test pattern with the bit value in the corresponding bit position in the second test pattern. The method merges subsequent test patterns that increase fault coverage with the second test pattern.

Abstract: A method for test pattern compression generates a first test pattern comprising a plurality of bits. The method identifies bits comprising a don't-care bit value in the first test pattern and replaces the identified bit values with random bit values, to generate a second test pattern. The method determines a fault coverage level of the second test pattern. In the event the determined fault coverage level of the second test pattern exceeds a predetermined individual test pattern fault coverage level, for at least one bit position in the second test pattern corresponding to a replaced identified bit value and detecting at least one fault, the method exchanges the don't care value in the bit position in the first test pattern with the bit value in the corresponding bit position in the second test pattern. The method merges subsequent test patterns that increase fault coverage with the second test pattern.

Abstract: A device for fault testing in a microprocessor chip provides a LBIST circuit which has a first reference signature. A loading unit is further provided for receiving and outputting a set of masking data. A file unit connected to the loading unit is yet further provided for receiving the masking data. A masking unit connected to the file unit is yet further provided for generating a second reference signature based on the masking data from the file unit and a scanning data from a scan string in the chip. And, a signature logic connected to the output of the masking unit is yet further provided for compressing the second reference signature and inputting the compressed second reference signature to the LBIST circuit, wherein the compressed second reference signature replaces the first reference signature.

Abstract: A method and apparatus for pipelining clock control signals across a chip. The present invention avoids the need for multiple clock distribution systems by allowing clock controls for clock stopping, scanning, and debugging to be distributed to all local clock buffers through pipelined non-scan latches. The test control pipeline latches may be routed along with the clock through the clock receiver, the central clock buffer, and the sector buffer areas of the chip. A relatively low speed testing mechanism may be used to drive the testing of the chip externally. The test clock is synchronized with a free-running clock on the chip to allow the circuit to be operated at speed during the testing of the chip. During boundary scan, the pipelined controls are forced to static levels which are active levels for scanning. Non-pipelined signals control the boundary scan operation based directly on the TCK clock defined in the IEEE 1149.1 boundary scan standard.

Abstract: A device for fault testing in a microprocessor chip provides a LBIST circuit which has a first reference signature. A loading unit is further provided for receiving and outputting a set of masking data. A file unit connected to the loading unit is yet further provided for receiving the masking data. A masking unit connected to the file unit is yet further provided for generating a second reference signature based on the masking data from the file unit and a scanning data from a scan string in the chip. And, a signature logic connected to the output of the masking unit is yet further provided for compressing the second reference signature and inputting the compressed second reference signature to the LBIST circuit, wherein the compressed second reference signature replaces the first reference signature.

Abstract: A method and apparatus for pipelining clock control signals across a chip. The present invention avoids the need for multiple clock distribution systems by allowing clock controls for clock stopping, scanning, and debugging to be distributed to all local clock buffers through pipelined non-scan latches. The test control pipeline latches may be routed along with the clock through the clock receiver, the central clock buffer, and the sector buffer areas of the chip. A relatively low speed testing mechanism may be used to drive the testing of the chip externally. The test clock control signals are synchronized with a free-running clock on the chip to allow the circuit to be operated at speed during the testing of the chip.

Abstract: A fault-tolerant computer system having shadow registers for storing the contents of a primary array into a shadow array at the completion of a stored instruction execution. This is accomplished in one clock cycle with all registers being shadowed simultaneously. During rollback of execution steps for a checkpoint retry, the shadow register files provide a signal cycle unload of the shadow array into the primary array. LSSD latches are used in the shadow register file.

Abstract: The improved register file includes an array of storage cells arranged in columns and rows, each column having a pair of bit lines for writing into the cell. Each storage cell includes a flip-flop cell having a first storage node connected to a respective read line which is unique for that cell. A read address latch has an enabling input connected to the master clock signal which is the same master clock signal for the LSSD logic on the integrated circuit chip. The read address latch applies its decoded output to a multiplexer which selects those read lines coming from one of the rows of storage cells in the array, and applies those selected read lines to an output storage cell array. The output storage cell array is enabled by a slave clock signal which is the same slave clock signal employed in the LSSD logic on the same integrated circuit chip. The output storage cell array stores the data from the selected read lines out of the multiplexer.