Abstract: A programming circuit of a phase change memory cell includes a controllable current generator to supply a programming pulse and an internal control unit coupled to the controllable current generator for stepwise modifying the programming pulse. The internal control unit, in turn, includes a control signal generator to provide the controllable current generator with a plurality of control signals. An oscillator provides a time reference signal and a driving module drives the control signal generator based on the time reference signal. As a result, a programming pulse with stepwise adjustable slope can be produced, including such a pulse with different leading and trailing edges.

Abstract: A programming circuit of a phase change memory cell includes a controllable current generator to supply a programming pulse and an internal control unit coupled to the controllable current generator for stepwise modifying the programming pulse. The internal control unit, in turn, includes a control signal generator to provide the controllable current generator with a plurality of control signals. An oscillator provides a time reference signal and a driving module drives the control signal generator based on the time reference signal. As a result, a programming pulse with stepwise adjustable slope can be produced, including such a pulse with different leading and trailing edges.

Abstract: Embodiments of an inductive charge pump are generally described herein. Other embodiments may be described and claimed.

Abstract: Embodiments of an inductive charge pump are generally described herein. Other embodiments may be described and claimed.

Abstract: A word line decode circuit may include three devices, a first p-type transistor, a first n-type transistor and a second n-type transistor together with a shared (with other word line decoding circuits) p-type transistor make up a “distributed” NOR gate. The first p-type transistor and the first n-type transistor may be toggled via the lowest level decode signal. To select a wordline, this low level decode signal may be low as well as a signal provided to the gate of the shared p-type transistor. The signal to the gate of the shared p-type transistor may be an output of a ratioed logic level shifter.

Abstract: A memory array includes a coupled controller for controlling the writing to, reading from and erasure of memory cells and blocks of memory cells within the memory array. The controller is operable during an erase process to determine and reduce odd/even wordline offset. The controller operates on separately settable odd/even wordline erase voltages, which are adjusted to affect offset.

Abstract: A memory array includes a coupled controller for controlling the writing to, reading from and erasure of memory cells and blocks of memory cells within the memory array. The controller is operable during an erase process to determine and reduce odd/even wordline offset. The controller operates on separately settable odd/even wordline erase voltages, which are adjusted to affect offset.

Abstract: A method for voltage detection and lockout. The method of one embodiment first compares a reference voltage to a supply voltage to determine whether the voltage supply voltage is greater than the reference voltage. The reference voltage is validated by determining whether the reference voltage is at least a valid voltage potential. An unlock signal is generated if the supply voltage is greater than the reference voltage and if the reference voltage is valid.

Abstract: A system includes an inductive element, at least one switch, an output stage and a circuit. The switch(es) is coupled to the inductive element to generate switching cycles. The switch(es) energizes and de-energizes the inductive element to generate each switching cycle. The output stage provides an output voltage. The circuit couples the output stage to the inductive element in response to a first set of the switching cycles and decouples the output stage from the inductive element in response to a second set of the switching cycles. The first set of switching cycles do not overlap the second set of switching cycles in time.

Abstract: A system includes an inductive element, at least one switch, an output stage and a circuit. The switch(es) is coupled to the inductive element to generate switching cycles. The switch(es) energizes and de-energizes the inductive element to generate each switching cycle. The output stage provides an output voltage. The circuit couples the output stage to the inductive element in response to a first set of the switching cycles and decouples the output stage from the inductive element in response to a second set of the switching cycles. The first set of switching cycles do not overlap the second set of switching cycles in time.

Abstract: A method for voltage detection and lockout. The method of one embodiment first compares a reference voltage to a supply voltage to determine whether the voltage supply voltage is greater than the reference voltage. The reference voltage is validated by determining whether the reference voltage is at least a valid voltage potential. An unlock signal is generated if the supply voltage is greater than the reference voltage and if the reference voltage is valid.

Abstract: A method for voltage detection and lockout. The method of one embodiment first compares a reference voltage to a supply voltage to determine whether the voltage supply voltage is greater than the reference voltage. The reference voltage is validated by determining whether the reference voltage is at least a valid voltage potential. An unlock signal is generated if the supply voltage is greater than the reference voltage and if the reference voltage is valid.

Abstract: Methods and apparatus for determining the state of a memory cell having more than two possible states are disclosed. For a first embodiment, the state of a flash cell having n states, where n is a power of 2, is determined by selectively comparing the threshold voltage V.sub.t of a selected memory cell to (n-1) reference voltages. For every two states, a single comparator is provided such that the total number of comparators is equal to the number of bits stored in the memory cell.

Abstract: A method and circuitry are described that permit one to utilize a partially functional integrated circuit memory. A memory array is segregated into separate blocks that can each be isolated to minimize the amount of the memory array rendered unusable by a defect. Circuitry is also provided to program memory cells within the array to one of at least three amounts of charge and thereby increase the amount of storage provided by the remaining functional blocks.

Abstract: Methods and apparatus for determining the state of a memory cell having more than two possible states are disclosed. For a first embodiment, the state of a flash cell having n states, where n is a power of 2, is determined by selectively comparing the threshold voltage V.sub.t of a selected memory cell to (n-1) reference voltages. For every two states, a single comparator is provided such that the total number of comparators is equal to the number of bits stored in the memory cell.

Abstract: A method for storing a charge on memory devices which includes the steps of providing a first charging pulse to a memory device to charge the device to a first level less than a final level; testing the value of the charge to determine whether the charge is greater than the first level; if the value of the charge is less than the first level, providing a second set of charging pulses to the memory device, each of the pulses of the second set of pulses having a duration which is a fraction of the duration of the first pulse and a value sufficient to charge the device to the first level; testing the value of the charge to determine whether the charge is greater than the first level after each pulse of the second set of pulses; and once the charge has tested greater than the first level, providing a third set of charging pulses to terminals of the memory device, each of the pulses of the third set of pulses having a duration which is a fraction of the duration of the pulses of the second set of pulses and a valu

Abstract: A method for storing a charge on memory devices which includes the steps of providing a first charging pulse to a memory device to charge the device to a first level less than a final level; testing the value of the charge to determine whether the charge is greater than the first level; if the value of the charge is less than the first level, providing a second set of charging pulses to the memory device, each of the pulses of the second set of pulses having a duration which is a fraction of the duration of the first pulse and a value sufficient to charge the device to the first level; testing the value of the charge to determine whether the charge is greater than the first level after each pulse of the second set of pulses; and once the charge has tested greater than the first level, providing a third set of charging pulses to terminals of the memory device, each of the pulses of the third set of pulses having a duration which is a fraction of the duration of the pulses of the second set of pulses and a valu

Abstract: A voltage regulation circuit that includes a sample and hold circuit for sampling an input voltage and for holding a reference voltage generated in response to the input voltage. The sample and hold circuit includes a capacitor that holds the reference voltage. The voltage regulation circuit also includes a regulator circuit coupled to the capacitor of the sample and hold circuit. The regulator circuit outputs an output voltage using the reference voltage supplied by the capacitor. The voltage regulation circuit may be used to provide a high precision programming voltage for programming memory cells having two or more analog states.

Abstract: A circuit for providing a regulated output voltage from a charge pump circuit while utilizing very low amounts of power, the circuit including a clock circuit for providing clock pulses to operate the charge pump circuit to produce an output voltage, a bias circuit for monitoring the output voltage of the charge pump and furnishing signals for enabling the clock circuit in response to an insufficient output voltage, and circuitry for enabling the bias circuit during a fraction of the total operating time available to the charge pump.

Abstract: A voltage regulation circuit that includes a sample and hold circuit for sampling an input voltage and for holding a reference voltage generated in response to the input voltage. The sample and hold circuit includes a capacitor that holds the reference voltage. The voltage regulation circuit also includes a regulator circuit coupled to the capacitor of the sample and hold circuit. The regulator circuit outputs an output voltage using the reference voltage supplied by the capacitor. The voltage regulation circuit may be used to provide a high precision programming voltage for programming memory cells having two or more analog states.