Abstract: Integrated circuit clock circuitry includes several clock nodes at different locations on a chip. Each node includes a clock wave input, a clock wave output and feedback circuitry for maintaining a predetermined phase relation between clock waves at the clock wave inputs and outputs. The clock wave input of one of the nodes is directly responsive to a clock wave of a clock wave source. A clock coupling circuit connected between each of the clock wave inputs (except the clock wave input of the node directly responsive to the clock wave source) and each of the clock wave outputs couples clock waves from the clock wave output of a first node to a clock wave input of a second node. Each of the coupling circuits includes feedback circuitry for maintaining a predetermined phase relation between clock waves the first node supplies to the coupling circuit and derived by the coupling circuit.

Abstract: A clock buffer circuit having a reduced propagation delay therethrough. The clock buffer circuit has a clock input for receiving an initial clock pulse thereto, and a clock output for transmitting a buffered clock pulse therethrough. A first driver chain arrangement of transistors is coupled with the clock input and the clock output for switching the buffered clock pulse from a low voltage level to a high voltage level. A second driver chain arrangement of transistors is coupled with the clock input and the clock output for switching the buffered clock pulse from the high voltage level to the low voltage level. A holder circuit and a first and trigger circuit for the second driver chain are also included.

Abstract: A clock circuit on an integrated circuit chip includes a driver having an output for deriving an output clock wave responsive to a clock wave of a clock wave source, a clock line having a first end coupled to the output of the driver, and a receiver having an input coupled to a second end of the clock line. The receiver has a resistive input impedance causing the clock line carrying the output clock wave to the input of the receiver to present to the driver output an impedance having a resistance-capacitance time constant that is a relatively small fraction of a period of the clock wave.

Abstract: Clock circuitry on an integrated circuit chip includes a differential buffer with common-mode rejection circuitry. The differential buffer includes first and second DC paths, each including semiconductor devices connected in cascode circuits. A tap of the first path supplies bias voltage to control electrodes of devices of the first and second paths. Control electrodes of devices in the cascode circuits of the first and second paths are connected to be biased by opposite power supply voltages of the buffer.

Abstract: A clock circuit on an integrated circuit chip includes a driver having an output for deriving an output clock wave responsive to a clock wave of a clock wave source, a clock line having a first end coupled to the output of the driver, and a receiver having an input coupled to a second end of the clock line. The receiver has a resistive input impedance causing the clock line carrying the output clock wave to the input of the receiver to present to the driver output an impedance having a resistance-capacitance time constant that is a relatively small fraction of a period of the clock wave.

Abstract: A termination structure is shown whereby multiple transmission lines designed to have the same intrinsic impedance and same delay are driven from a central node. The central node is driven by a driver and calibration resistor connected in series to produce a drive impedance that is equal to the parallel combination of the intrinsic impedances of the multiple transmission lines. At the other end of the multiple transmission lines is a receiver and a feedback circuit. The feedback circuit provides a modest amount of positive feedback from the output of the receiver to the input of the receiver. This positive feedback prevents the output of the receiver from being affected by small reflections and perturbations that result from mismatches among the multiple transmission lines.

Abstract: A ring-type signal controlled oscillator comprising a series of active delay elements, each including a respective differential pair of transistors. The inputs and outputs of the differential pair transistors are interconnected in a closed ring to produce oscillations at a frequency determined by the delay of each delay element. The differential pair of transistors further has a pair of current source inputs for controlling an amount of delay of the delay element, and a pair of load inputs for stabilizing the amount of delay. The invention advantageously provides high frequency operation with substantially symmetric rise and fall time, while limiting spread in oscillation frequency and spread in amplitude in relation to fabrication process variability and power supply variability.