Abstract: Some example memory systems include a load and store unit (LSU) operable to load a memory reference. The LSU may include an alignment register, a current memory reference register, and a vector register. The memory system may include a memory coupled to the LSU. The memory may be operable to store a memory reference. The memory reference may be aligned or unaligned in the memory, and the LSU may be operable to efficiently load both unaligned and aligned memory references. Some example memory systems include a load and store unit (LSU) operable to store to the memory at a memory address. The LSU may be operable to efficiently store to both unaligned and aligned memory addresses. The LSU may perform loads and stores in forward and reverse stride.

Abstract: Some example memory systems include a load and store unit (LSU) operable to load a memory reference. The LSU may include an alignment register, a current memory reference register, and a vector register. The memory system may include a memory coupled to the LSU. The memory may be operable to store a memory reference. The memory reference may be aligned or unaligned in the memory, and the LSU may be operable to efficiently load both unaligned and aligned memory references. Some example memory systems include a load and store unit (LSU) operable to store to the memory at a memory address. The LSU may be operable to efficiently store to both unaligned and aligned memory addresses. The LSU may perform loads and stores in forward and reverse stride.

Abstract: Clock distribution network and method for dynamically changing clock frequency in digital processing system are provided. The method includes receiving, at a first clock input of a first divider, a frequency signal from a clock source and receiving, at a state machine, a first status signal from the first divider, the first status signal indicating a first number of clock edges that have transpired from a first phase reference clock edge of the first divider. The method includes asserting, using the state machine, a first hold signal at a first hold input of the first divider, the first hold signal suspending operation of the first divider when asserted and after asserting the first hold signal, latching a new first divider value into the first divider. The method includes de-asserting, using the state machine, the first hold signal subsequent to latching the new first divider value into the first divider.

Abstract: Clock distribution network and method for dynamically changing clock frequency in digital processing system are provided. The method includes receiving, at a first clock input of a first divider, a frequency signal from a clock source and receiving, at a state machine, a first status signal from the first divider, the first status signal indicating a first number of clock edges that have transpired from a first phase reference clock edge of the first divider. The method includes asserting, using the state machine, a first hold signal at a first hold input of the first divider, the first hold signal suspending operation of the first divider when asserted and after asserting the first hold signal, latching a new first divider value into the first divider. The method includes de-asserting, using the state machine, the first hold signal subsequent to latching the new first divider value into the first divider.

Abstract: A method and apparatus for adaptable phase training of high frequency clock signaling for data capture is provided. A state machine synchronizes a first selection signal to a delay multiplexer and a second selection signal to a digital block demultiplexer to sequentially select a targeted pair of the static storage elements for each of a plurality of phase-delayed data strobe clock signals. Read back data from an external memory captured by the static storage elements is compared to known valid data. The state machine determines which of the plurality of phase-delayed data strobe clock signals resulted in known valid data being captured by the static storage elements based on the comparison. The state machine selects one of the plurality of phase-delayed data strobe clock signals that resulted in valid data being captured as a read clock signal for a memory controller to capture subsequent read data from the external memory.

Abstract: A method and apparatus for mitigating electromagnetic noise in an electronic device. The method includes generating a trigger clock signal at a first frequency, and generating a second clock signal at a second frequency. The second frequency is higher than the first frequency. The method also includes receiving an input signal with a converter circuit, detecting an event based on the trigger clock signal, and predicting a time for a conversion of the input signal based on the detected event. The method further includes blanking the second clock signal for a predetermined period based on the predicted time for a conversion.

Abstract: A real-time reconfigurable input/output interface of a controller and a method of reconfiguring the same. The reconfigurable interface enables the controller to communicate with a plurality of peripheral digital subsystem blocks, and includes an input/output interface, a profile memory, and a state machine. The input/output interface includes a plurality of data lines including a shared portion that are shared among the plurality of peripheral digital subsystem blocks. The profile memory stores a plurality of interface profiles, each interface profile defining a configuration of the input/output interface to communicate with an associated one of the peripheral blocks. The state machine is coupled to the profile memory to receive interface profiles and to the input/output interface. In response to each request to communicate with a particular peripheral block, the state machine configures the input/output interface according to the interface profile associated with the particular peripheral block.