Patents by Inventor Johnson Chan Limqueco

Johnson Chan Limqueco has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Delay estimation for restructuring
    Patent number: 6672776
    Abstract: Provided are a method, article of manufacture, and apparatus for estimating delays of networks. An automated design system comprises a computer configured to identify a critical path in a network, calculate a delay for the technology-mapped version of the network, calculate a delay for the technology-independent version of the network, calculate a scale factor from the technology-mapped and technology-independent delays, and apply the scale factor to all the delays in the technology-independent network.
    Type: Grant
    Filed: March 14, 1997
    Date of Patent: January 6, 2004
    Assignee: Cadence Design Systems
    Inventors: Johnson Chan Limqueco, Hong Li, Krishna Belkhale, Devadas Varma
  • Delay estimation for restructuring the technology independent circuit
    Patent number: 6543037
    Abstract: Provided are a method, article of manufacture, and apparatus for estimating delays of networks. An automated design system comprises a computer configured to identify a critical path in a network, calculate a delay for the technology-mapped version of the network, calculate a delay for the technology-independent version of the network, calculate a scale factor from the technology-mapped and technology-independent delays, and apply the scale factor to all the delays in the technology-independent network.
    Type: Grant
    Filed: December 16, 1999
    Date of Patent: April 1, 2003
    Assignee: Cadence Design Systems, Inc.
    Inventors: Johnson Chan Limqueco, Hong Li, Krishna Belkhale, Devadas Varma
  • Method and apparatus for performing both negative and positive slack time budgeting and for determining a definite required constraint during integrated circuit design
    Patent number: 6401231
    Abstract: Two time budgeting techniques are provided that are suitable for early and late integrated circuit design phases, respectively. During the early design phase, both the positive and negative slack paths are time budgeted, such that a positive slack path cannot become a negative slack path after budget generation. If all the budget constraints are met by resynthesis for all circuit modules, then the technique guarantees that the final design, when assembled, meets all time constraints. During the late design phase, convergence is guaranteed. Further, synthesis runs for sub-modules focus initially on the worst critical path.
    Type: Grant
    Filed: April 25, 1997
    Date of Patent: June 4, 2002
    Assignee: Cadence Design Systems, Inc.
    Inventors: Krishna Belkhale, Johnson Chan Limqueco