Abstract: There is described a data processing apparatus with a binary multiplication capability. The apparatus has an arithmetic and logic unit (ALU) and a operand register. The operand register is divided into two portions, the first of which can be shifted while the second is loaded in parallel. For multiplication, the first portion is used to hold a multiplier and to receive the least significant bits of the result, while the second portion receives the most significant bits of the result. The invention avoids the need for a separate shift register to hold the multiplier. The described apparatus also has a look-ahead facility, for selecting the next bit of the multiplier ahead of its requirement, so that it is immediately available when required.

Abstract: A pipelined data processor is described, which obeys a sequence of instructions each with a read phase in which an operand is read from a memory, an execute phase in which an operation is performed by an execution unit, and a write phase in which a result is written into the memory. The phases of successive instructions are overlapped, and each instruction is stepped on to its next phase at the end of each clock beat. Each clock beat is divided into a write sub-beat followed by two read sub-beats. The write address for each instruction is stored in a write address register and is compared with each read or write address applied to the memory. When these addresses match, the output of the execution unit is either written into the memory (if the match occurs during a write sub-beat) or fed back to the execution unit as an operand (if the match occurs during a read sub-beat).

Abstract: In a data storage apparatus, memory chips are arranged in groups, each group having an address bus which is connected to the address inputs of all the chips in that group. Each address bus is terminated at both ends by circuits which perform the dual function of suppressing reflections and checking the addresses.Because reflections are suppressed, the time taken to address the store is reduced. One of the termination circuits in each group is arranged to compare the address on the bus with that on the bus in the adjacent group; the other circuit compares the address with a predetermined value.