Abstract: An integrated circuit device includes a first under mold layer and a second under mold layer each extending in a first direction and spaced apart from each other in a second direction, perpendicular to the first direction; an under metal line between the first under mold layer and the second under mold layer and extending in the first direction; an intermediate mold layer on the first under mold layer and the second under mold layer and separated from the under metal line by an air gap; and a via contact on the under metal line and extending through an opening in the intermediate mold layer, the via contact comprising a first portion adjacent to the under metal line having a first width in the first direction that is wider than a second width in the second direction.

Abstract: Integrated circuit devices and methods of forming the same are provided. The integrated circuit devices may include a substrate; an insulator on an upper surface of the substrate; a transistor between the substrate and the insulator, the transistor comprising: channel layers that are spaced apart from each other in a first direction that is perpendicular to the upper surface of the substrate; and a gate structure on the channel layers and the insulator, wherein a width of the insulator in a second direction that is parallel with the upper surface of the substrate is equal or substantially equal to a width of an uppermost one of the channel layers in the second direction.

Abstract: According to some embodiments of the inventive concepts, an integrated circuit device may be provided. The integrated circuit device may include a lower conductive line, a conductive via on the lower conductive line and a stopping pattern between the lower conductive line and the conductive via. A side surface of the stopping pattern may be aligned with the side surface of the lower conductive line and the side surface of the conductive via.

Abstract: Methods of forming a back-end-of-line (BEOL) region of an integrated circuit (IC) device are provided. A method of forming a BEOL region of an IC device includes forming a metal layer on a lower via. The method includes forming a photo key in an upper portion of the metal layer. The method includes forming an insulating material on the photo key. Moreover, the method includes planarizing the insulating material and the metal layer that includes the photo key.

Abstract: Provided is a semiconductor device which includes: a base layer; a 1st metal line extended in a 1st direction on the base layer; a 2nd metal line extended in the 1st direction, and adjacent to the 1st metal line at a same level, on the base layer; and a metal jumper, between the 1st metal line and the 2nd metal line, at the same level, wherein the metal jumper connects the 1st metal line and the 2nd metal line.

Abstract: Provided is a semiconductor device which includes: a base layer; a 1st metal line on the base layer; a 1st capping structure on the 1st metal line; and an isolation structure surrounding the 1st metal line and the 1st capping structure, wherein the isolation structure and the 1st capping structure comprise different dielectric materials.

Abstract: Provided is a semiconductor device which includes: a base layer; and at least one metal line on the base layer, wherein each of the at least one metal line comprise a 1st metal structure and a 2nd metal structure on the 1st metal structure, the 1st metal structure is formed through a direct etching process, and the 2nd metal structure is formed through a damascene process.

Abstract: Provided is a semiconductor device which includes: a base layer; a 1st metal line and a 2nd metal extended in a 1st direction and arranged in a 2nd direction, intersecting the 1st direction, in a 1st layer above the base layer; and a bridge metal pattern extended in the 2nd direction to connect the 1st metal line and the 2nd metal line in a 2nd layer immediately above the 1st layer.

Abstract: A sacrificial layer is formed to cover the gate structures. The sacrificial layer is patterned to form a first opening in the sacrificial layer. A preliminary contact is formed in the first opening and the sacrificial layer is selectively removed. An insulating layer is formed to cover the gate structures and to expose the preliminary contact. The preliminary contact is removed to form a second opening in the insulating layer, and then a contact is formed in the second opening.

Abstract: A method of forming a semiconductor device includes forming a gate electrode on a substrate, forming a first spacer on a sidewall of the gate electrode, forming a second spacer on the first spacer, and forming a capping pattern on top surfaces of the gate electrode, the first spacer and the second spacer. An outer sidewall of the second spacer is vertically aligned with a sidewall of the capping pattern.

Abstract: A method of forming a semiconductor device includes forming a gate electrode on a substrate, forming a first spacer on a sidewall of the gate electrode, forming a second spacer on the first spacer, and forming a capping pattern on top surfaces of the gate electrode, the first spacer and the second spacer. An outer sidewall of the second spacer is vertically aligned with a sidewall of the capping pattern.

Abstract: A sacrificial layer is formed to cover the gate structures. The sacrificial layer is patterned to form a first opening in the sacrificial layer. A preliminary contact is formed in the first opening and the sacrificial layer is selectively removed. An insulating layer is formed to cover the gate structures and to expose the preliminary contact. The preliminary contact is removed to form a second opening in the insulating layer, and then a contact is formed in the second opening.