Abstract: A design structure for a pipeline electronic processor device may be embodied in a machine readable medium for designing, manufacturing or testing a processor integrated circuit. The design structure may embody a pipeline electronic circuit that enables power conservation in the stages of the pipeline via a simulation that identifies clock-gating opportunities among the stages of the pipeline. In one embodiment, simulation results assist a designer in the design of the pipeline electronic circuit design structure to achieve power conservation by incorporating clock-gating circuitry among the stages of the pipeline at clock gating opportunity locations that the simulation identifies.

Abstract: A pipeline electronic circuit and design methodology enables power conservation in the stages of the pipeline via a simulation that identifies clock-gating opportunities among the stages of the pipeline. In one embodiment, simulation results assist a designer in the design of the pipeline electronic circuit to achieve power conservation by incorporating clock-gating circuitry among the stages of the pipeline at clock gating opportunity locations that the simulation identifies.

Abstract: A design structure for a pipeline electronic processor device may be embodied in a machine readable medium for designing, manufacturing or testing a processor integrated circuit. The design structure may embody a pipeline electronic circuit that enables power conservation in the stages of the pipeline via a simulation that identifies clock-gating opportunities among the stages of the pipeline. In one embodiment, simulation results assist a designer in the design of the pipeline electronic circuit design structure to achieve power conservation by incorporating clock-gating circuitry among the stages of the pipeline at clock gating opportunity locations that the simulation identifies.

Abstract: A pipeline electronic circuit and design methodology enables power conservation in the stages of the pipeline via a simulation that identifies clock-gating opportunities among the stages of the pipeline. In one embodiment, simulation results assist a designer in the design of the pipeline electronic circuit to achieve power conservation by incorporating clock-gating circuitry among the stages of the pipeline at clock gating opportunity locations that the simulation identifies.

Abstract: A logic design development tool including a converting unit configured to convert a plurality of different circuit design languages into a common intermediate format, and an executing unit configured to execute the common intermediate format so as to perform a design simulation of a circuit defined by the circuit design languages.

Abstract: A logic design development tool including a converting unit configured to convert a plurality of different circuit design languages into a common intermediate format, and an executing unit configured to execute the common intermediate format so as to perform a design simulation of a circuit defined by the circuit design languages.