Patents by Inventor JoHyun Bae

JoHyun Bae has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9349666
    Abstract: An integrated circuit packaging system includes: providing a base substrate; applying a molded under-fill on the base substrate; forming a substrate contact extender through the molded under-fill and in direct contact with the base substrate; mounting a stack device over the molded under-fill; attaching a coupling connector from the substrate contact extender to the stack device; and forming a base encapsulation on the stack device, the substrate contact extender, and encapsulating the coupling connector.
    Type: Grant
    Filed: March 31, 2014
    Date of Patent: May 24, 2016
    Assignee: STATS ChipPAC Ltd.
    Inventors: JoHyun Bae, In Sang Yoon, DaeSik Choi
  • Patent number: 9330945
    Abstract: An integrated circuit package system with multi-chip module is provided including: providing an upper substrate having an upper chip thereon; positioning a lower chip under the upper chip, the lower chip having bottom interconnects thereon; encapsulating the upper chip and the lower chip with a chip encapsulant on the upper substrate with the bottom interconnects exposed; mounting the lower chip over a lower substrate with a gap between the chip encapsulant and the lower substrate; and filling the gap with a package encapsulant or chip attach adhesive.
    Type: Grant
    Filed: September 18, 2007
    Date of Patent: May 3, 2016
    Assignee: STATS ChipPAC Ltd.
    Inventors: Sungmin Song, SeungYun Ahn, JoHyun Bae, Jong-Woo Ha
  • Patent number: 9093391
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a base substrate; connecting a base component directly to the base substrate; mounting a stack component over the base component; attaching a flattened exposed interconnect directly on the stack component; and applying an encapsulant over the stack component with a portion of the flattened exposed interconnect exposed.
    Type: Grant
    Filed: September 17, 2009
    Date of Patent: July 28, 2015
    Assignee: STATS ChipPAC Ltd.
    Inventors: SeungYun Ahn, JoHyun Bae, SangJin Lee
  • Patent number: 9093392
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a package substrate having a package substrate bottom side, a package substrate top side, and a package substrate window; mounting a base integrated circuit over the package substrate, the base integrated circuit having a base inactive side and a base active side facing the package substrate top side; attaching a lower internal connector to the base active side and the package substrate bottom side, the lower internal connector through the package substrate window; forming an upper insulation conformal to the base integrated circuit and the package substrate top side, the upper insulation having an upper insulation top side; and forming a peripheral through-insulation connector through the upper insulation, the peripheral through-insulation connector having a peripheral connector bottom side directly on the package substrate top side and a peripheral connector top side coplanar with the upper insulation top side.
    Type: Grant
    Filed: December 10, 2010
    Date of Patent: July 28, 2015
    Assignee: STATS ChipPAC Ltd.
    Inventors: SungWon Cho, JoHyun Bae, DaeSik Choi, DongSoo Moon
  • Patent number: 8772916
    Abstract: An integrated circuit package system that includes: a support structure including an electrical contact; a solder mask over the support structure, the solder mask including a solder mask flange, the solder mask flange directly on a support structure first surface; an integrated circuit over the support structure; and encapsulant over the integrated circuit and in contact with the solder mask flange. A mold system that includes a first mold having a projection along a first mold bottom surface, the projection between a first cavity and a recess.
    Type: Grant
    Filed: June 28, 2012
    Date of Patent: July 8, 2014
    Assignee: Stats Chippac Ltd.
    Inventors: Ki Youn Jang, Sungmin Song, JoHyun Bae
  • Patent number: 8698297
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a base substrate; applying a molded under-fill on the base substrate; forming a substrate contact extender through the molded under-fill and in direct contact with the base substrate; mounting a stack device over the molded under-fill; attaching a coupling connector from the substrate contact extender to the stack device; and forming a base encapsulation on the stack device, the substrate contact extender, and encapsulating the coupling connector.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: April 15, 2014
    Assignee: STATS ChipPAC Ltd.
    Inventors: JoHyun Bae, In Sang Yoon, DaeSik Choi
  • Patent number: 8699232
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a substrate; mounting an interposer having a top interposer surface over the substrate; attaching an interposer pad extension to the top interposer surface, the interposer pad extension having an extension contact surface and a lower contact surface, the surface area of the extension contact surface being smaller than the surface area of the lower contact surface; and forming a package encapsulation on the substrate, the interposer, and the interposer pad extension, the package encapsulation having a recess exposing the top interposer surface, the interposer pad extension embedded only in the package encapsulation.
    Type: Grant
    Filed: September 20, 2011
    Date of Patent: April 15, 2014
    Assignee: Stats Chippac Ltd.
    Inventors: A Leam Choi, DeokKyung Yang, JoHyun Bae
  • Patent number: 8674516
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a first substrate; attaching vertical interconnects along a periphery of the first substrate; mounting an integrated circuit over the first substrate, the integrated circuit surrounded by the vertical interconnects; and mounting a second substrate directly on the vertical interconnects and the integrated circuit.
    Type: Grant
    Filed: June 22, 2011
    Date of Patent: March 18, 2014
    Assignee: Stats Chippac Ltd.
    Inventors: Byung Joon Han, In Sang Yoon, JoHyun Bae
  • Patent number: 8643181
    Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a rounded interconnect on a package carrier having an integrated circuit attached thereto, the rounded interconnect having an actual center; forming an encapsulation over the package carrier covering the rounded interconnect; removing a portion of the encapsulation over the rounded interconnect with an ablation tool; calculating an estimated center of the rounded interconnect; aligning the ablation tool over the estimated center; and exposing a surface area of the rounded interconnect with the ablation tool.
    Type: Grant
    Filed: March 24, 2010
    Date of Patent: February 4, 2014
    Assignee: STATS ChipPAC Ltd.
    Inventors: JoHyun Bae, SeongHun Mun, SeungYun Ahn
  • Patent number: 8569869
    Abstract: A method of manufacture of an integrated circuit packaging system includes: mounting an integrated circuit over a package carrier; mounting a rounded interconnect on the package carrier; mounting a conductive shield over the package carrier, the conductive shield having an elevated portion and a hole adjacent to the elevated portion with the elevated portion over the integrated circuit and the rounded interconnect exposed from the hole; and forming an encapsulation between the conductive shield and the package carrier with the rounded interconnect exposed.
    Type: Grant
    Filed: March 23, 2010
    Date of Patent: October 29, 2013
    Assignee: Stats Chippac Ltd.
    Inventors: HyungSang Park, A Leam Choi, JoHyun Bae
  • Patent number: 8501535
    Abstract: A method for manufacturing an integrated circuit package system includes: connecting an integrated circuit die with a bottom connection structure; placing an adhesive encapsulation over the integrated circuit die and the bottom connection structure with the bottom connection structure exposed; and placing a top connection structure over the adhesive encapsulation at an opposing side to the bottom connection structure.
    Type: Grant
    Filed: January 31, 2011
    Date of Patent: August 6, 2013
    Assignee: Stats Chippac Ltd.
    Inventors: Sungmin Song, SeungYun Ahn, JoHyun Bae
  • Patent number: 8497575
    Abstract: A method of manufacture of a semiconductor packaging system includes: providing a base substrate having edges; mounting an electrical interconnect on the base substrate; and applying an encapsulant having a reference marker and an opening over the electrical interconnect, the reference marker around the electrical interconnect based on physical locations of the edges.
    Type: Grant
    Filed: February 22, 2010
    Date of Patent: July 30, 2013
    Assignee: STATS Chippac Ltd.
    Inventors: In Sang Yoon, JoHyun Bae, DeokKyung Yang
  • Patent number: 8461680
    Abstract: An integrated circuit packaging system includes: a package carrier; an integrated circuit attached to the package carrier; a rounded interconnect on the package carrier; and an encapsulation over the package carrier covering the integrated circuit and exposing the rounded interconnect having a characteristic free of denting.
    Type: Grant
    Filed: October 12, 2011
    Date of Patent: June 11, 2013
    Assignee: Stats Chippac Ltd.
    Inventors: JoHyun Bae, DaeSik Choi, SungWon Cho
  • Publication number: 20130075926
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a base substrate; applying a molded under-fill on the base substrate; forming a substrate contact extender through the molded under-fill and in direct contact with the base substrate; mounting a stack device over the molded under-fill; attaching a coupling connector from the substrate contact extender to the stack device; and forming a base encapsulation on the stack device, the substrate contact extender, and encapsulating the coupling connector.
    Type: Application
    Filed: September 23, 2011
    Publication date: March 28, 2013
    Inventors: JoHyun Bae, In Sang Yoon, DaeSik Choi
  • Publication number: 20130070438
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a substrate; mounting an interposer having a top interposer surface over the substrate; attaching an interposer pad extension to the top interposer surface, the interposer pad extension having an extension contact surface and a lower contact surface, the surface area of the extension contact surface being smaller than the surface area of the lower contact surface; and forming a package encapsulation on the substrate, the interposer, and the interposer pad extension, the package encapsulation having a recess exposing the top interposer surface, the interposer pad extension embedded only in the package encapsulation.
    Type: Application
    Filed: September 20, 2011
    Publication date: March 21, 2013
    Inventors: A Leam Choi, DeokKyung Yang, JoHyun Bae
  • Publication number: 20120326331
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a first substrate; attaching vertical interconnects along a periphery of the first substrate; mounting an integrated circuit over the first substrate, the integrated circuit surrounded by the vertical interconnects; and mounting a second substrate directly on the vertical interconnects and the integrated circuit.
    Type: Application
    Filed: June 22, 2011
    Publication date: December 27, 2012
    Inventors: Byung Joon Han, In Sang Yoon, JoHyun Bae
  • Patent number: 8304900
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a substrate; attaching an integrated circuit device to the substrate; forming a stud interconnect having stacked studs, the stud interconnect on the substrate and having a contact surface and a crown surface on an end of the stud interconnect opposite the substrate; applying an encapsulation over the integrated circuit die, over the stud interconnect, and over the substrate; and forming a cavity in the encapsulation over the stud interconnect, the contact surface and the crown surface exposed in the cavity.
    Type: Grant
    Filed: August 11, 2010
    Date of Patent: November 6, 2012
    Assignee: Stats Chippac Ltd.
    Inventors: Ki Youn Jang, YoungJoon Kim, JoHyun Bae
  • Publication number: 20120267801
    Abstract: An integrated circuit package system that includes: a support structure including an electrical contact; a solder mask over the support structure, the solder mask including a solder mask flange, the solder mask flange directly on a support structure first surface; an integrated circuit over the support structure; and encapsulant over the integrated circuit and in contact with the solder mask flange. A mold system that includes a first mold having a projection along a first mold bottom surface, the projection between a first cavity and a recess.
    Type: Application
    Filed: June 28, 2012
    Publication date: October 25, 2012
    Inventors: Ki Youn Jang, Sungmin Song, JoHyun Bae
  • Patent number: 8252615
    Abstract: An integrated circuit package system that includes: providing a support structure including an integrated circuit and an electrical contact adjacent thereto; providing a first mold having a first cavity with a projection and a recess for collecting flash; engaging the first mold on the support structure with the first cavity over at least a portion of the integrated circuit and the projection and the recess between the at least a portion of the integrated circuit and the electrical contact; and injecting encapsulation material into the first cavity.
    Type: Grant
    Filed: December 22, 2006
    Date of Patent: August 28, 2012
    Assignee: Stats Chippac Ltd.
    Inventors: Ki Youn Jang, Sungmin Song, JoHyun Bae
  • Patent number: 8232141
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a substrate; forming a conductive pillar, having substantially parallel vertical sides, in direct contact with the substrate; mounting an integrated circuit to the substrate beside a conductive pillar location; and encapsulating the integrated circuit with an encapsulation having a top surface formed for the conductive pillar to extend beyond.
    Type: Grant
    Filed: April 5, 2011
    Date of Patent: July 31, 2012
    Assignee: Stats Chippac Ltd.
    Inventors: DaeSik Choi, JoHyun Bae, Junghoon Shin