Patents by Inventor Joji Fujimori
Joji Fujimori has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9425088Abstract: A semiconductor device includes: a substrate; a semiconductor element installed on the substrate so that a surface formed with an electrode is directed to the substrate; a chip capacitor installed on the substrate; and a conductive material covering a rear surface opposite to the surface of the semiconductor element and joining to one terminal electrode of the chip capacitor.Type: GrantFiled: April 13, 2013Date of Patent: August 23, 2016Assignee: SOCIONEXT INC.Inventors: Takumi Ihara, Seiji Ueno, Joji Fujimori, Yasunori Fujimoto
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Patent number: 8564121Abstract: A semiconductor device includes: a substrate; a semiconductor element installed on the substrate so that a surface formed with an electrode is directed to the substrate; a chip capacitor installed on the substrate; and a conductive material covering a rear surface opposite to the surface of the semiconductor element and joining to one terminal electrode of the chip capacitor.Type: GrantFiled: September 23, 2011Date of Patent: October 22, 2013Assignee: Fujitsu Semiconductor LimitedInventors: Takumi Ihara, Seiji Ueno, Joji Fujimori, Yasunori Fujimoto
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Publication number: 20120153448Abstract: A semiconductor device includes: a substrate; a semiconductor element installed on the substrate so that a surface formed with an electrode is directed to the substrate; a chip capacitor installed on the substrate; and a conductive material covering a rear surface opposite to the surface of the semiconductor element and joining to one terminal electrode of the chip capacitor.Type: ApplicationFiled: September 23, 2011Publication date: June 21, 2012Applicant: c/o FUJITSU SEMICONDUCTOR LIMITEDInventors: Takumi Ihara, Seiji Ueno, Joji Fujimori, Yasunori Fujimoto
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Patent number: 7879713Abstract: A mounting method of a semiconductor element whereby the semiconductor element is mounted on a wiring board via an outside connection projection electrode not containing lead (Pb), the mounting method includes a step of applying a reflow heating process for connecting the outside connection projection electrode of the semiconductor element and the wiring board and then cooling the connected semiconductor element and wiring board at a cooling rate equal to and lower than 0.5° C./s.Type: GrantFiled: January 17, 2007Date of Patent: February 1, 2011Assignee: Fujitsu Semiconductor LimitedInventors: Joji Fujimori, Seiki Sakuyama, Toshiya Akamatsu
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Patent number: 7871917Abstract: To provide a low-cost, easy-to-use, and efficient method for manufacturing a semiconductor device, which eliminates the need for the formation or removal of barrier metals upon formation of bumps, and a high-performance semiconductor device with fine bumps arranged at a narrow pitch. The method includes: forming a plurality of electrode pads 12 on one surface of a semiconductor substrate 10; forming insulating layers (e.g., inorganic insulating layer 14 and organic insulating layer 16) to cover the perimeter of each electrode pad 12; selectively forming a mask layer 20 on the insulating layers 14 and 16; cleaning the surface of the electrode pads 12 which is not covered with the insulating layers 14 and 16; forming external terminals 46 in regions defined by the insulating layers 14 and 16 and mask layer 20 so that they are in contact with the electrode pads 12; and removing the mask layer 20.Type: GrantFiled: May 31, 2006Date of Patent: January 18, 2011Assignee: Fujitsu Semiconductor LimitedInventor: Joji Fujimori
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Publication number: 20100105173Abstract: A method for manufacturing a semiconductor device by mounting a semiconductor element on a circuit board, the semiconductor element having a first electrode made of a first material on a semiconductor substrate, the circuit board having a second electrode made of a second material on an insulating substrate, the method includes forming a connecting member on the first electrode, a melting point of the connecting member being lower than a melting point of the first material, placing the semiconductor element on the circuit board, so as to face the connecting member toward the second electrode, and connecting the first electrode and the second electrode, so as to interpose the connecting member between the first electrode and the second electrode, at a temperature that is lower than the melting point of the first material and higher than the melting point of the connecting member.Type: ApplicationFiled: October 21, 2009Publication date: April 29, 2010Applicant: FUJITSU MICROELECTRONICS LIMITEDInventor: Joji Fujimori
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Publication number: 20080124834Abstract: A mounting method of a semiconductor element whereby the semiconductor element is mounted on a wiring board via an outside connection projection electrode not containing lead (Pb), the mounting method includes a step of applying a reflow heating process for connecting the outside connection projection electrode of the semiconductor element and the wiring board and then cooling the connected semiconductor element and wiring board at a cooling rate equal to and lower than 0.5° C./s.Type: ApplicationFiled: January 17, 2007Publication date: May 29, 2008Applicant: FUJITSU LIMITEDInventors: Joji Fujimori, Seiki Sakuyama, Toshiya Akamatsu
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Publication number: 20070197016Abstract: To provide a low-cost, easy-to-use, and efficient method for manufacturing a semiconductor device, which eliminates the need for the formation or removal of barrier metals upon formation of bumps, and a high-performance semiconductor device with fine bumps arranged at a narrow pitch. The method includes: forming a plurality of electrode pads 12 on one surface of a semiconductor substrate 10; forming insulating layers (e.g., inorganic insulating layer 14 and organic insulating layer 16) to cover the perimeter of each electrode pad 12; selectively forming a mask layer 20 on the insulating layers 14 and 16; cleaning the surface of the electrode pads 12 which is not covered with the insulating layers 14 and 16; forming external terminals 46 in regions defined by the insulating layers 14 and 16 and mask layer 20 so that they are in contact with the electrode pads 12; and removing the mask layer 20.Type: ApplicationFiled: May 31, 2006Publication date: August 23, 2007Applicant: FUJITSU LIMITEDInventor: Joji Fujimori
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Patent number: 6897142Abstract: A method of forming a solder ball includes the steps of forming an electrode pad on a substrate, forming an insulating layer having a first opening at a position of the electrode pad, filling the first opening with solder paste that include solder and first resin, and applying a heating process to the solder paste so as to form a solder ball on the electrode pad and to form a cured resin member of the first resin across a border between the electrode pad and the substrate.Type: GrantFiled: August 1, 2003Date of Patent: May 24, 2005Assignee: Fujitsu LimitedInventors: Joji Fujimori, Ichiro Yamaguchi
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Publication number: 20040046252Abstract: A method of forming a solder ball includes the steps of forming an electrode pad on a substrate, forming an insulating layer having a first opening at a position of the electrode pad, filling the first opening with solder paste that include solder and first resin, and applying a heating process to the solder paste so as to form a solder ball on the electrode pad and to form a cured resin member of the first resin across a border between the electrode pad and the substrate.Type: ApplicationFiled: August 1, 2003Publication date: March 11, 2004Applicant: FUJITSU LIMITEDInventors: Joji Fujimori, Ichiro Yamaguchi
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Patent number: 6689639Abstract: A method of making a semiconductor device includes a resin film forming step for forming a resin film on a semiconductor substrate 10 provided with electrode portions 11 to cover the electrode portions 11, an opening forming step for forming openings in the resin film at locations corresponding to the electrode portions 11, a loading step for loading a bump material in the openings, a bump forming step for forming bumps 41 in the openings by heating, and a removing step for removing the resin film.Type: GrantFiled: November 12, 2002Date of Patent: February 10, 2004Assignee: Fujitsu LimitedInventors: Seiki Sakuyama, Masayuki Ochiai, Ichiro Yamaguchi, Joji Fujimori
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Publication number: 20030096494Abstract: A method of making a semiconductor device includes a resin film forming step for forming a resin film on a semiconductor substrate 10 provided with electrode portions 11 to cover the electrode portions 11, an opening forming step for forming openings in the resin film at locations corresponding to the electrode portions 11, a loading step for loading a bump material in the openings, a bump forming step for forming bumps 41 in the openings by heating, and a removing step for removing the resin film.Type: ApplicationFiled: November 12, 2002Publication date: May 22, 2003Applicant: FUJITSU LIMITEDInventors: Seiki Sakuyama, Masayuki Ochiai, Ichiro Yamaguchi, Joji Fujimori
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Patent number: 6218281Abstract: A semiconductor substrate is prepared which has a principal surface, an exposed pad made of conductive material being formed in a partial area of the principal surface, and the other area of the principal surface being covered with a first insulating film. A base conductive film is formed on the first insulating film and the pad. A photoresist film having a thickness of 50 &mgr;m or thicker is formed on the base conductive film. An opening is formed through the photoresist film in an area corresponding to the pad to expose a partial surface area of the base conductive film. A conductive bump electrode is deposited on the base conductive film exposed on a bottom of the opening. The photoresist film is removed. This method is suitable for making a fine pitch between bump electrodes.Type: GrantFiled: November 16, 1998Date of Patent: April 17, 2001Assignee: Fujitsu LimitedInventors: Eiji Watanabe, Hirohisa Matsuki, Kenichi Kado, Kenichi Nagashige, Masanori Onodera, Kunio Kodama, Hiroyuki Yoda, Joji Fujimori, Minoru Nakada, Yutaka Makino
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Patent number: 5831441Abstract: A test board used for testing a semiconductor device provided with projection electrodes includes a main board and testing electrodes. The testing electrodes are provided on the main board, each projecting upwardly from the main board. When the semiconductor device is tested, the testing electrodes are electrically connected to the projection electrodes by insertion of the testing electrodes into the projection electrodes. The semiconductor device is mounted on the main board to test the semiconductor device through the testing electrodes.Type: GrantFiled: March 8, 1996Date of Patent: November 3, 1998Assignee: Fujitsu LimitedInventors: Toshiyuki Motooka, Syuichirou Takahasi, Tatsuharu Matsuda, Kunio Kodama, Joji Fujimori, Shigeki Harada, Masataka Mizukoshi, Masashi Takenaka, Tatsuro Yamashita