Patents by Inventor Joji Fujimori

Joji Fujimori has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9425088
    Abstract: A semiconductor device includes: a substrate; a semiconductor element installed on the substrate so that a surface formed with an electrode is directed to the substrate; a chip capacitor installed on the substrate; and a conductive material covering a rear surface opposite to the surface of the semiconductor element and joining to one terminal electrode of the chip capacitor.
    Type: Grant
    Filed: April 13, 2013
    Date of Patent: August 23, 2016
    Assignee: SOCIONEXT INC.
    Inventors: Takumi Ihara, Seiji Ueno, Joji Fujimori, Yasunori Fujimoto
  • Patent number: 8564121
    Abstract: A semiconductor device includes: a substrate; a semiconductor element installed on the substrate so that a surface formed with an electrode is directed to the substrate; a chip capacitor installed on the substrate; and a conductive material covering a rear surface opposite to the surface of the semiconductor element and joining to one terminal electrode of the chip capacitor.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: October 22, 2013
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Takumi Ihara, Seiji Ueno, Joji Fujimori, Yasunori Fujimoto
  • Publication number: 20120153448
    Abstract: A semiconductor device includes: a substrate; a semiconductor element installed on the substrate so that a surface formed with an electrode is directed to the substrate; a chip capacitor installed on the substrate; and a conductive material covering a rear surface opposite to the surface of the semiconductor element and joining to one terminal electrode of the chip capacitor.
    Type: Application
    Filed: September 23, 2011
    Publication date: June 21, 2012
    Applicant: c/o FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Takumi Ihara, Seiji Ueno, Joji Fujimori, Yasunori Fujimoto
  • Patent number: 7879713
    Abstract: A mounting method of a semiconductor element whereby the semiconductor element is mounted on a wiring board via an outside connection projection electrode not containing lead (Pb), the mounting method includes a step of applying a reflow heating process for connecting the outside connection projection electrode of the semiconductor element and the wiring board and then cooling the connected semiconductor element and wiring board at a cooling rate equal to and lower than 0.5° C./s.
    Type: Grant
    Filed: January 17, 2007
    Date of Patent: February 1, 2011
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Joji Fujimori, Seiki Sakuyama, Toshiya Akamatsu
  • Patent number: 7871917
    Abstract: To provide a low-cost, easy-to-use, and efficient method for manufacturing a semiconductor device, which eliminates the need for the formation or removal of barrier metals upon formation of bumps, and a high-performance semiconductor device with fine bumps arranged at a narrow pitch. The method includes: forming a plurality of electrode pads 12 on one surface of a semiconductor substrate 10; forming insulating layers (e.g., inorganic insulating layer 14 and organic insulating layer 16) to cover the perimeter of each electrode pad 12; selectively forming a mask layer 20 on the insulating layers 14 and 16; cleaning the surface of the electrode pads 12 which is not covered with the insulating layers 14 and 16; forming external terminals 46 in regions defined by the insulating layers 14 and 16 and mask layer 20 so that they are in contact with the electrode pads 12; and removing the mask layer 20.
    Type: Grant
    Filed: May 31, 2006
    Date of Patent: January 18, 2011
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Joji Fujimori
  • Publication number: 20100105173
    Abstract: A method for manufacturing a semiconductor device by mounting a semiconductor element on a circuit board, the semiconductor element having a first electrode made of a first material on a semiconductor substrate, the circuit board having a second electrode made of a second material on an insulating substrate, the method includes forming a connecting member on the first electrode, a melting point of the connecting member being lower than a melting point of the first material, placing the semiconductor element on the circuit board, so as to face the connecting member toward the second electrode, and connecting the first electrode and the second electrode, so as to interpose the connecting member between the first electrode and the second electrode, at a temperature that is lower than the melting point of the first material and higher than the melting point of the connecting member.
    Type: Application
    Filed: October 21, 2009
    Publication date: April 29, 2010
    Applicant: FUJITSU MICROELECTRONICS LIMITED
    Inventor: Joji Fujimori
  • Publication number: 20080124834
    Abstract: A mounting method of a semiconductor element whereby the semiconductor element is mounted on a wiring board via an outside connection projection electrode not containing lead (Pb), the mounting method includes a step of applying a reflow heating process for connecting the outside connection projection electrode of the semiconductor element and the wiring board and then cooling the connected semiconductor element and wiring board at a cooling rate equal to and lower than 0.5° C./s.
    Type: Application
    Filed: January 17, 2007
    Publication date: May 29, 2008
    Applicant: FUJITSU LIMITED
    Inventors: Joji Fujimori, Seiki Sakuyama, Toshiya Akamatsu
  • Publication number: 20070197016
    Abstract: To provide a low-cost, easy-to-use, and efficient method for manufacturing a semiconductor device, which eliminates the need for the formation or removal of barrier metals upon formation of bumps, and a high-performance semiconductor device with fine bumps arranged at a narrow pitch. The method includes: forming a plurality of electrode pads 12 on one surface of a semiconductor substrate 10; forming insulating layers (e.g., inorganic insulating layer 14 and organic insulating layer 16) to cover the perimeter of each electrode pad 12; selectively forming a mask layer 20 on the insulating layers 14 and 16; cleaning the surface of the electrode pads 12 which is not covered with the insulating layers 14 and 16; forming external terminals 46 in regions defined by the insulating layers 14 and 16 and mask layer 20 so that they are in contact with the electrode pads 12; and removing the mask layer 20.
    Type: Application
    Filed: May 31, 2006
    Publication date: August 23, 2007
    Applicant: FUJITSU LIMITED
    Inventor: Joji Fujimori
  • Patent number: 6897142
    Abstract: A method of forming a solder ball includes the steps of forming an electrode pad on a substrate, forming an insulating layer having a first opening at a position of the electrode pad, filling the first opening with solder paste that include solder and first resin, and applying a heating process to the solder paste so as to form a solder ball on the electrode pad and to form a cured resin member of the first resin across a border between the electrode pad and the substrate.
    Type: Grant
    Filed: August 1, 2003
    Date of Patent: May 24, 2005
    Assignee: Fujitsu Limited
    Inventors: Joji Fujimori, Ichiro Yamaguchi
  • Publication number: 20040046252
    Abstract: A method of forming a solder ball includes the steps of forming an electrode pad on a substrate, forming an insulating layer having a first opening at a position of the electrode pad, filling the first opening with solder paste that include solder and first resin, and applying a heating process to the solder paste so as to form a solder ball on the electrode pad and to form a cured resin member of the first resin across a border between the electrode pad and the substrate.
    Type: Application
    Filed: August 1, 2003
    Publication date: March 11, 2004
    Applicant: FUJITSU LIMITED
    Inventors: Joji Fujimori, Ichiro Yamaguchi
  • Patent number: 6689639
    Abstract: A method of making a semiconductor device includes a resin film forming step for forming a resin film on a semiconductor substrate 10 provided with electrode portions 11 to cover the electrode portions 11, an opening forming step for forming openings in the resin film at locations corresponding to the electrode portions 11, a loading step for loading a bump material in the openings, a bump forming step for forming bumps 41 in the openings by heating, and a removing step for removing the resin film.
    Type: Grant
    Filed: November 12, 2002
    Date of Patent: February 10, 2004
    Assignee: Fujitsu Limited
    Inventors: Seiki Sakuyama, Masayuki Ochiai, Ichiro Yamaguchi, Joji Fujimori
  • Publication number: 20030096494
    Abstract: A method of making a semiconductor device includes a resin film forming step for forming a resin film on a semiconductor substrate 10 provided with electrode portions 11 to cover the electrode portions 11, an opening forming step for forming openings in the resin film at locations corresponding to the electrode portions 11, a loading step for loading a bump material in the openings, a bump forming step for forming bumps 41 in the openings by heating, and a removing step for removing the resin film.
    Type: Application
    Filed: November 12, 2002
    Publication date: May 22, 2003
    Applicant: FUJITSU LIMITED
    Inventors: Seiki Sakuyama, Masayuki Ochiai, Ichiro Yamaguchi, Joji Fujimori
  • Patent number: 6218281
    Abstract: A semiconductor substrate is prepared which has a principal surface, an exposed pad made of conductive material being formed in a partial area of the principal surface, and the other area of the principal surface being covered with a first insulating film. A base conductive film is formed on the first insulating film and the pad. A photoresist film having a thickness of 50 &mgr;m or thicker is formed on the base conductive film. An opening is formed through the photoresist film in an area corresponding to the pad to expose a partial surface area of the base conductive film. A conductive bump electrode is deposited on the base conductive film exposed on a bottom of the opening. The photoresist film is removed. This method is suitable for making a fine pitch between bump electrodes.
    Type: Grant
    Filed: November 16, 1998
    Date of Patent: April 17, 2001
    Assignee: Fujitsu Limited
    Inventors: Eiji Watanabe, Hirohisa Matsuki, Kenichi Kado, Kenichi Nagashige, Masanori Onodera, Kunio Kodama, Hiroyuki Yoda, Joji Fujimori, Minoru Nakada, Yutaka Makino
  • Patent number: 5831441
    Abstract: A test board used for testing a semiconductor device provided with projection electrodes includes a main board and testing electrodes. The testing electrodes are provided on the main board, each projecting upwardly from the main board. When the semiconductor device is tested, the testing electrodes are electrically connected to the projection electrodes by insertion of the testing electrodes into the projection electrodes. The semiconductor device is mounted on the main board to test the semiconductor device through the testing electrodes.
    Type: Grant
    Filed: March 8, 1996
    Date of Patent: November 3, 1998
    Assignee: Fujitsu Limited
    Inventors: Toshiyuki Motooka, Syuichirou Takahasi, Tatsuharu Matsuda, Kunio Kodama, Joji Fujimori, Shigeki Harada, Masataka Mizukoshi, Masashi Takenaka, Tatsuro Yamashita