Abstract: A corrective device for an inverter output voltage error in which a current sensor is connected in series with the output of an inverter, the polarity of current detected by the current sensor is discriminated by a polarity decision current, a value corresponding to an input D.C. voltage is found by a D.C. voltage sensor, a signal with the polarity of the value inverted according to the discriminated result delivered from the polarity decision current is generted by a polarity inverter circuit, and the signal is applied as a correction signal to the PWM (pulse-width modulation) circuit of the inverter so as to correct the output voltage error.

Abstract: A memory unit for tracing data receives and records data from a data bus together with a set of marking bits or a predetermined code identifying a selected address detected by an address detecting and pulse generating circuit. The data and code are temporarily recorded in a tracing memory which may be a FIFO shift register or a RAM which is addressed by a counter incremented by each pulse from the pulse generating circuit.

Abstract: A speed detection apparatus for detecting speed of electric equipment on the basis of a sampling interval so as to stably operate a variable speed control system connected thereto.The sampling interval is varied in accordance with an input current to be supplied to the electric equipment to compensate for different current pulsations due to different modes of operation and the torques produced at different load conditions.

Abstract: The present invention relates to a running speed detector comprising:a pulse encoder which generates pulses of a frequency proportional to the running speed of a rotary member;pulse period counting device for counting the periods of pulses having said frequency relying upon clock signals;memory for storing ounted values of periods counted by said pulse period counting means; andand a calculating device which receives pulses having said frequency, which calculates the sum of n latest counted values that have been counted already after the arrival of each of said pulses or after the arrival of a predetermined number of pulses, and which calculates the running speed that varies in proportion to a ratio of the number n of counted values of periods to said sum of counted values of periods.

Abstract: An A/D converter comprising a multiplexer for selecting one of multi-channel analog signals sequentially, an A/D converting circuit for converting a selected analog signal into digital data, a memory for storing converted data in certain address locations, and a control circuit operating on the multiplexer to select an input and addressing the memory in unison in response to an external trigger signal.