Abstract: A multi-CPU programmable controller which operates to access one of a plurality of I/O interface units through a common I/O bus for controlling one of a plurality of equipments each connected to each associated one of the I/O interface units. The programmable controller includes a pair of controllers, each of the pair including an individual CPU for generating an access signal for selectively accessing one of said I/O interface units through the common I/O bus for control thereof within one bus cycle. Each of the pair of controllers operates in accordance with a specific program independently from each other. The programmable controller further includes a base board for mounting controllers together with the common I/O bus as well as the I/O interface units: bus arbitrating device, provided on the base board, for generating a single sampling clock.

Abstract: A programmable controller includes a main processor connected to I/O and peripheral devices for sequential control thereof in a programmed manner. The main processor is associated with a system memory which stores an operating system for the main processor as well as provides a work area used in the operation thereof. A source instruction memory is provided to store a source program for control of the I/O and peripheral devices. The source program is compiled by the main processor into a program including corresponding reduced instructions and stored in an coprocessor instruction memory. A coprocessor is included to retrieve the instructions from the coprocessor instruction memory to execute the instructions in a pipeline mode and in parallel with the execution of the main processor. A data memory is provided for instruction execution of the coprocessor.