Patents by Inventor Joji Nakane

Joji Nakane has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6907088
    Abstract: In a contactless IC card that performs envelope detection on an ASK-modulated carrier wave and demodulates the carrier wave to recover data piggybacked thereon, demodulation is suspended during periods where there is no possibility of a change of a data value (from data 0 to data 1, or from data 1 to data 0) in the digital data piggybacked on the carrier wave. In so doing, incorrect data recovery can be prevented even when noise arises in power supply voltage waveform due to power consumption of an internal memory or the like.
    Type: Grant
    Filed: September 19, 2000
    Date of Patent: June 14, 2005
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Joji Nakane, Tatsumi Sumi
  • Patent number: 6747907
    Abstract: In a power supply voltage detection circuit using a reference potential generation circuit, as represented by a band gap reference circuit according to a prior art, the correction of dispersion in the detection level cannot be carried out after the completion of diffusion and assembly. Therefore, a power supply voltage detection circuit 4 is provided with a reference potential generation circuit 1, a divided voltage potential generation circuit 2 and a differential amplification circuit 3 for comparing the divided voltage potential to the reference potential. Furthermore, a ferroelectric memory 5 which stores correction data for correcting the reference potential, a data latch circuit 7 for storing correction data that has been read out, and a microcomputer logic unit 6 for controlling ferroelectric memory 5 as well as data latch circuit 7 are provided. The reference potential is altered according to correction data so that dispersion in the power supply voltage detection level is reduced.
    Type: Grant
    Filed: December 2, 2002
    Date of Patent: June 8, 2004
    Assignee: Matsushita Electric Industrial Co. Ltd.
    Inventors: Yoshitaka Mano, Joji Nakane
  • Patent number: 6659352
    Abstract: A semiconductor integrated circuit which obtains a driving power from a carrier onto which data has been piggybacked, the semiconductor integrated circuit being characterized by demodulating data by correctly discriminating it even when the obtained power supply voltage has become overvoltage, and characterized by effectively using the power supplied by the carrier. The semiconductor integrated circuit includes: a two-voltage rectifier circuit as a power source circuit 111; a voltage regulator circuit 112 which exercises a control so that a power with a higher voltage (VDDH) used for demodulating data does not exceed a certain voltage value; a resistor 141; and a capacitor 142. With this construction, the voltage input to a regulator circuit 1121 as the reference voltage changes in correspondence to the change in voltage VDDH which is caused by the change in amplitude.
    Type: Grant
    Filed: May 31, 2000
    Date of Patent: December 9, 2003
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hiroaki Asada, Joji Nakane, Tatsumi Sumi, Taketoshi Matsuura, Atsuo Inoue
  • Publication number: 20030103405
    Abstract: In a power supply voltage detection circuit using a reference potential generation circuit, as represented by a band gap reference circuit according to a prior art, the correction of dispersion in the detection level cannot be carried out after the completion of diffusion and assembly. Therefore, a power supply voltage detection circuit 4 is provided with a reference potential generation circuit 1, a divided voltage potential generation circuit 2 and a differential amplification circuit 3 for comparing the divided voltage potential to the reference potential. Furthermore, a ferroelectric memory 5 which stores correction data for correcting the reference potential, a data latch circuit 7 for storing correction data that has been read out, and a microcomputer logic unit 6 for controlling ferroelectric memory 5 as well as data latch circuit 7 are provided. The reference potential is altered according to correction data so that dispersion in the power supply voltage detection level is reduced.
    Type: Application
    Filed: December 2, 2002
    Publication date: June 5, 2003
    Inventors: Yoshitaka Mano, Joji Nakane
  • Patent number: 6038160
    Abstract: A semiconductor memory device of nonvolatile ferroelectric capable of stable operation without loss of logic voltage "L" data of the memory cell in rewriting operation. To achieve, for example, as shown in FIG. 1, diodes 1, 2 are connected to cell plate lines 39, 40. Therefore, in rewriting operation, if there is a parasitic resistance 3 in the cell plate line 39, it is possible to prevent occurrence of transient phenomenon of temporary transition of the cell plate line 39 to an excessive negative voltage (for example, lower than -1V) which may cause loss of data.
    Type: Grant
    Filed: May 28, 1998
    Date of Patent: March 14, 2000
    Assignee: Matsushita Electronics Corporation
    Inventors: Joji Nakane, Nobuyuki Moriwaki