Patents by Inventor Joji Philip

Joji Philip has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230342323
    Abstract: An interface for coupling an agent to a fabric supports a load/store interconnect protocol, where the I/O interconnect protocol includes a flit mode and a non-flit mode. A set of flit mode header formats are used when in the flit mode and a set of non-flit mode header formats are used when in the non-flit mode, the set of non-flit mode header formats including one or more non-flit mode fields. Interface logic determines that a link is trained to the non-flit mode and generates a header according to the set of flit mode header formats, where the header includes a field to indicate that a corresponding packet originated as a non-flit mode packet. One or more fields of the set of flit mode header formats are repurposed in the header to carry the one or more non-flit mode fields before sending the modified header over the interface.
    Type: Application
    Filed: June 30, 2023
    Publication date: October 26, 2023
    Inventors: Mohannad Fahim Ali, Swadesh Choudhary, Joji Philip, David J. Harriman
  • Publication number: 20230059954
    Abstract: Embodiments of the disclosed techniques disclose methods for planning an indoor radio network for a building. In one embodiment, a method comprises preprocessing an image of a floor plan of the building; generating a radio propagation map for the floor plan using the preprocessed image; and determining an indoor radio transmitter distribution for the floor plan using the radio propagation map.
    Type: Application
    Filed: May 11, 2020
    Publication date: February 23, 2023
    Applicant: Telefonaktiebolaget LM Ericsson (publ)
    Inventors: Taesuh PARK, Chun-Hao LIU, Hun CHANG, Joji PHILIP, Thalanayar MUTHUKUMAR, Michael MARAGOUDAKIS
  • Publication number: 20230041036
    Abstract: Methods, systems, and storage media are disclosed to estimate a count of indoor radio transmitters for a building, where the indoor radio transmitters are to be planned to build an indoor cellular network within the building. In one embodiment, a method comprises obtaining (310) locational information of the building in a database based on a query; extracting (312) features external to the building based on the locational information of the building, wherein the features external to the building capture characteristics about the building that are observable from outside of the building; and estimating (314) the count of the indoor radio transmitters for the building using the extracted features and a pre-trained model.
    Type: Application
    Filed: February 12, 2021
    Publication date: February 9, 2023
    Applicant: Telefonaktiebolaget LM Ericsson (publ)
    Inventors: Taesuh PARK, Jianfu ZHANG, Joji PHILIP
  • Publication number: 20210373075
    Abstract: A system comprising a network-on-chip (NOC) fabric comprising a plurality of routes to communicate data between a plurality of agents; a plurality of built-in self-test (BIST) generators, wherein a BIST generator of the plurality of BIST generators is coupled between an agent of the plurality of agents and the NOC fabric and is to transmit at least one test pattern through the NOC fabric; and a plurality of BIST checkers, wherein a BIST checker of the plurality of BIST checkers is coupled between the agent of the plurality of agents and the NOC fabric and is to receive at least one test pattern through the NOC fabric from at least one of the plurality of BIST generators and to verify whether the at least one test pattern was transmitted correctly through the NOC fabric.
    Type: Application
    Filed: August 11, 2021
    Publication date: December 2, 2021
    Applicant: Intel Corporation
    Inventors: Dawn Maxon, Eric A. Norige, Joji Philip, William John Bainbridge, Joseph B. Rowlands
  • Patent number: 11144457
    Abstract: Aspects of the present disclosure relate to page locality based memory access request processing in a network-on-chip (NoC) architecture. In an example implementation, the proposed method includes determining, at an arbitrator, while selecting a NoC agent from a plurality of NoC agents for request processing for a forthcoming round, if current NoC agent of current round is processing a packet stream and if said packet stream is completely processed at the end of said current round, wherein processing of the packet stream enables cluster requests to be processed at same part of said memory and enhances page locality; and re-selecting, at said arbitrator, said current NoC agent as the NoC agent for the forthcoming round if said packet stream processing is not completed at the end of said current round, so as to enable said current NoC agent to complete processing of said packet stream in said forthcoming round.
    Type: Grant
    Filed: January 25, 2019
    Date of Patent: October 12, 2021
    Assignee: NETSPEED SYSTEMS, INC.
    Inventors: Joseph Rowlands, Joji Philip
  • Patent number: 10983910
    Abstract: The present disclosure relates to a bandwidth weighting mechanism based NoC configuration/constructions for packet routing. In an aspect, the present disclosure relates to a method for packet routing in a circuit architecture, wherein the method includes the steps of managing, at a router of the circuit architecture, one or more catch-up bits, each of the one or more catch-up bits indicating that the router has reset a round of round-robin based packet routing without allowing an agent corresponding to the each of the one or more catch-up bits to complete its respective round; and allowing, by the router, the agent to continue its respective round in catch-up state such that upon completion of the respective round, the agent is switched to normal state.
    Type: Grant
    Filed: January 25, 2019
    Date of Patent: April 20, 2021
    Assignee: NETSPEED SYSTEMS, INC.
    Inventors: Joseph Rowlands, Joji Philip
  • Patent number: 10749811
    Abstract: Example implementations described herein are directed to a configurable Network on Chip (NoC) element that can be configured with a bypass that permits messages to pass through the NoC without entering the queue or arbitration. The configurable NoC element can also be configured to provide a protocol alongside the valid-ready protocol to facilitate valid-ready functionality across virtual channels.
    Type: Grant
    Filed: February 23, 2018
    Date of Patent: August 18, 2020
    Assignee: NetSpeed Systems, Inc.
    Inventors: Joseph Rowlands, Joji Philip, Sailesh Kumar, Nishant Rao
  • Patent number: 10735335
    Abstract: Example implementations described herein are directed to a configurable Network on Chip (NoC) element that can be configured with a bypass that permits messages to pass through the NoC without entering the queue or arbitration. The configurable NoC element can also be configured to provide a protocol alongside the valid-ready protocol to facilitate valid-ready functionality across virtual channels.
    Type: Grant
    Filed: February 23, 2018
    Date of Patent: August 4, 2020
    Assignee: NetSpeed Systems, Inc.
    Inventors: Joseph Rowlands, Joji Philip, Sailesh Kumar, Nishant Rao
  • Publication number: 20190258573
    Abstract: The present disclosure relates to a bandwidth weighting mechanism based NoC configuration/constructions for packet routing. In an aspect, the present disclosure relates to a method for packet routing in a circuit architecture, wherein the method includes the steps of managing, at a router of the circuit architecture, one or more catch-up bits, each of the one or more catch-up bits indicating that the router has reset a round of round-robin based packet routing without allowing an agent corresponding to the each of the one or more catch-up bits to complete its respective round; and allowing, by the router, the agent to continue its respective round in catch-up state such that upon completion of the respective round, the agent is switched to normal state.
    Type: Application
    Filed: January 25, 2019
    Publication date: August 22, 2019
    Inventors: Joseph ROWLANDS, Joji PHILIP
  • Publication number: 20190260504
    Abstract: Methods and example implementations described herein are directed to systems and methods for maintaining network-on-chip (NoC) safety and reliability. An aspect of the present disclosure relates to an network-on-chip (NoC)-based error correction system capable of supporting a network interface (NI) that transmits a flit between a transmission side (Tx) intellectual property (IP) element and a receiving side (Rx) IP element. The system includes an encoder configured to receive a k-bit flit from the Tx IP element and encodes the k-bit flit into n-bit data (where k and n denote any natural numbers), and a decoder configured to receive the n-bit data, decode the n-bit data into the k-bit flit, and output the k-bit flit, the decoder having an error correction circuit for correcting an error in the n-bit data. In an aspect, the error correction circuit comprises a multiple overlapping layers of coverage configured for the NoC transport infrastructure.
    Type: Application
    Filed: February 1, 2019
    Publication date: August 22, 2019
    Inventors: Joji Philip, Joseph Rowlands, Sailesh Kumar
  • Publication number: 20190258572
    Abstract: Aspects of the present disclosure relate to page locality based memory access request processing in a network-on-chip (NoC) architecture. In an example implementation, the proposed method includes determining, at an arbitrator, while selecting a NoC agent from a plurality of NoC agents for request processing for a forthcoming round, if current NoC agent of current round is processing a packet stream and if said packet stream is completely processed at the end of said current round, wherein processing of the packet stream enables cluster requests to be processed at same part of said memory and enhances page locality; and re-selecting, at said arbitrator, said current NoC agent as the NoC agent for the forthcoming round if said packet stream processing is not completed at the end of said current round, so as to enable said current NoC agent to complete processing of said packet stream in said forthcoming round.
    Type: Application
    Filed: January 25, 2019
    Publication date: August 22, 2019
    Inventors: Joseph ROWLANDS, Joji Philip
  • Patent number: 10355996
    Abstract: Systems and methods involving construction of a system interconnect in which different channels have different widths in numbers of bits. Example processes to construct such a heterogeneous channel NoC interconnect are disclosed herein, wherein the channel width may be determined based upon the provided specification of bandwidth and latency between various components of the system.
    Type: Grant
    Filed: October 21, 2014
    Date of Patent: July 16, 2019
    Inventors: Sailesh Kumar, Joji Philip, Eric Norige, Sundari Mitra
  • Patent number: 10027433
    Abstract: Example implementations described herein are directed to a micro-architecture of NoC router clocking which allows for a flexible Globally Asynchronous Locally Synchronous (GALS) implementation. The example implementations allow arbitrary clock domain partitions to be defined across the system. The example implementations further involve allowing the components of the NoC to be configured by the user through a NoC generation system to achieve the desired arbitrary clock domain partitioning.
    Type: Grant
    Filed: June 19, 2013
    Date of Patent: July 17, 2018
    Assignee: NETSPEED SYSTEMS
    Inventors: Joji Philip, Joseph Rowlands, Sailesh Kumar
  • Publication number: 20180191626
    Abstract: Example implementations described herein are directed to a configurable Network on Chip (NoC) element that can be configured with a bypass that permits messages to pass through the NoC without entering the queue or arbitration. The configurable NoC element can also be configured to provide a protocol alongside the valid-ready protocol to facilitate valid-ready functionality across virtual channels.
    Type: Application
    Filed: February 23, 2018
    Publication date: July 5, 2018
    Inventors: Joseph ROWLANDS, Joji PHILIP, Sailesh KUMAR, Nishant RAO
  • Publication number: 20180183721
    Abstract: Example implementations described herein are directed to a configurable Network on Chip (NoC) element that can be configured with a bypass that permits messages to pass through the NoC without entering the queue or arbitration. The configurable NoC element can also be configured to provide a protocol alongside the valid-ready protocol to facilitate valid-ready functionality across virtual channels.
    Type: Application
    Filed: February 23, 2018
    Publication date: June 28, 2018
    Inventors: Joseph ROWLANDS, Joji PHILIP, Sailesh KUMAR, Nishant RAO
  • Publication number: 20180183722
    Abstract: Example implementations described herein are directed to a configurable Network on Chip (NoC) element that can be configured with a bypass that permits messages to pass through the NoC without entering the queue or arbitration. The configurable NoC element can also be configured to provide a protocol alongside the valid-ready protocol to facilitate valid-ready functionality across virtual channels.
    Type: Application
    Filed: February 23, 2018
    Publication date: June 28, 2018
    Inventors: Joseph ROWLANDS, Joji PHILIP, Sailesh KUMAR, Nishant RAO
  • Publication number: 20180159786
    Abstract: Example implementations described herein are directed to a configurable Network on Chip (NoC) element that can be configured with a bypass that permits messages to pass through the NoC without entering the queue or arbitration. The configurable NoC element can also be configured to provide a protocol alongside the valid-ready protocol to facilitate valid-ready functionality across virtual channels.
    Type: Application
    Filed: December 1, 2017
    Publication date: June 7, 2018
    Inventors: Joseph Rowlands, Joji Philip, Sailesh Kumar, Nishant Rao
  • Patent number: 9825809
    Abstract: Aspects of the present disclosure relates to methods, computer readable mediums, and NoC architectures/systems/constructions that can automatically mark and configure some channel of a NoC as store-and-forward channels, and other channels of the NoC as cut-through channels, and can further resize the buffers/channels based on the given NoC specification and associated traffic profile. An aspect of the present disclosure relates to a method for configuring a first set of plurality of channels of a NoC as store-and-forward channels, and configuring a second set of plurality of channels of the NoC as cut-through channels based on the determination of idle cycles in a given NoC specification and associated traffic profile.
    Type: Grant
    Filed: May 29, 2015
    Date of Patent: November 21, 2017
    Assignee: NETSPEED SYSTEMS
    Inventors: Joji Philip, Sailesh Kumar
  • Patent number: 9781043
    Abstract: Systems and methods for automatically building a deadlock free inter-communication network in a multi-core system are described. The example implementations described herein involve automatically generating internal dependency specification of a system component based on dependencies between incoming/input and outgoing/output interface channels of the component. Dependencies between incoming and outgoing interface channels of the component can be determined by blocking one or more outgoing interface channels and evaluating impact of the blocked outgoing channels on the incoming interface channels. Another implementation described herein involves determining inter-component communication dependencies by measuring impact of a deadlock on the blocked incoming interface channels of one or more components to identify whether a dependency cycle is formed by blocked incoming interface channels.
    Type: Grant
    Filed: August 26, 2013
    Date of Patent: October 3, 2017
    Assignee: NetSpeed Systems
    Inventors: Sailesh Kumar, Eric Norige, Joji Philip, Joseph Rowlands
  • Patent number: 9774498
    Abstract: A network-on-chip configuration includes a first plurality of cores arranged in a two-dimensional mesh; a first plurality of routers, each of the first plurality of routers associated with a corresponding local one of the first plurality of cores, each of the first plurality of routers having a plurality of directional ports configured to provide connections to other ones of the first plurality of routers; a second plurality of cores disposed around a periphery of the two-dimensional mesh arrangement; and a second plurality of routers, each of the second plurality of routers associated with a corresponding local one of the second plurality of cores, and having a directional port configured to provide a connection to a neighboring one of the first plurality of routers.
    Type: Grant
    Filed: June 25, 2015
    Date of Patent: September 26, 2017
    Assignee: NetSpeed Systems
    Inventors: Sailesh Kumar, Eric Norige, Joji Philip, Mahmud Hassan, Sundari Mitra, Joseph Rowlands