Abstract: A cache memory control unit includes plural banks composing a cache memory, an address array for feeding a hit signal or a mishit signal indicating whether or not the corresponding data is stored in the cache memory in response to the access requests received from plural instruction processors couples to the cache memory, and a data transfer requester for sending out a data transfer request to the main storage in response to a mishit signal. Each of the banks includes a first stack for holding an access request according to the access request and the hit signal, and a transfer data monitor for monitoring the data sent out of the main storage according to the data transfer request for the main storage, accessing each of the banks based on the access request from the first stack if the data is not being sent, and sending out the data from the bank to any one of plural instruction processors.