Abstract: An adjustable kick voltage and an adjustable time duration are adjusted/set based on one or more conditions of a non-volatile memory. During an erase process, an erase voltage pulse is applied to a set of non-volatile memory cells of the non-volatile memory including driving an erase pulse voltage magnitude to an elevated voltage that is equal to a base erase voltage plus the adjusted kick voltage for the adjusted time duration and then reducing the erase pulse voltage magnitude to the base erase voltage for the remainder of the erase voltage pulse.

Abstract: To determine NAND memory blocks with an upper tail or a lower tail of select gate threshold voltage levels, a tail detection read is introduced into the erase process. To minimize the time penalty on the erase process, the tail detection read is only performed for a specified loop in the erase verify process. More specifically, in an erase process using an algorithm of a loop of applying an erase pulse followed by an erase verify operation, an erase loop count is maintained and incremented at each loop. If the block fails erase verify, before looping back for the next erase pulse a tail detection read is performed, but only if the erase loop count equals a specified value (which can be a settable parameter); otherwise, the tail detection read is not performed.

Abstract: An adjustable kick voltage and an adjustable time duration are adjusted/set based on one or more conditions of a non-volatile memory.

Abstract: A memory apparatus and operating method are provided. The apparatus includes drain-side select gate transistors for coupling to a drain-side of each of a plurality of memory holes of memory cells and configured to retain a transistor threshold voltage. The memory apparatus also includes a control means configured to perform a predetermined quantity of erase operations on the memory cells of at least one block of a die of the memory cells. The control means is also configured to report the die as failing in response to determining the transistor threshold voltage of one or more of the drain-side select gate transistors of the at least one block does not meet a predetermined criteria.

Abstract: In addition to word line related short circuits within the blocks of the array structure of a non-volatile memory device, such as NAND memory, word line related shorts can also occur in the routing for supplying the word lines of the memory blocks. Depending on the layout of the routing, some shorts for the word lines associated with one block can affect other blocks of the memory array. In particular, if the routing of a pair of adjacent local supply lines are adjacent to a global supply line, a short between the pair of adjacent local supply lines for one block can lead, through the global supply line, to defects in another of the block. Techniques are presented for detecting these layout related problematic word lines.

Abstract: In some situations, a leak on a wordline may be a localized problem that causes data loss in a block that contains the wordline. In other situations, such as when the leak occurs near a peripheral wordline routing area, the leak can affect the entire memory die. The storage system provided herein has a fatal wordline leak detector that determines the type of leak and, accordingly, whether just the block should be retired or whether related blocks should be retired.

Abstract: In addition to word line related short circuits within the blocks of the array structure of a non-volatile memory device, such as NAND memory, word line related shorts can also occur in the routing for supplying the word lines of the memory blocks. Depending on the layout of the routing, some shorts for the word lines associated with one block can affect other blocks of the memory array. In particular, if the routing of a pair of adjacent local supply lines are adjacent to a global supply line, a short between the pair of adjacent local supply lines for one block can lead, through the global supply line, to defects in another of the block. Techniques are presented for detecting these layout related problematic word lines.

Abstract: In some situations, a leak on a wordline may be a localized problem that causes data loss in a block that contains the wordline. In other situations, such as when the leak occurs near a peripheral wordline routing area, the leak can affect the entire memory die. The storage system provided herein has a fatal wordline leak detector that determines the type of leak and, accordingly, whether just the block should be retired or whether related blocks should be retired.