Abstract: A stage of a pipelined ADC used as a sub-ADC in a time-interleaved ADC is operated using a first set of clock signals, with a next stage being operated using a second set of clock signals. The first set and second set of clock signals are designed to cause the start of hold phases of the stage to occur earlier than the sample phases of the next stage. In an embodiment, the start of the hold phases is coincident with the end of an immediately preceding sample phase of the stage. As a result, more time is provided for the output of an amplifier used in the stage to settle to a final value, thus permitting use of a low speed amplifier and reduction in power consumption in the interleaved ADC. In an embodiment, the stage corresponds to an earliest stage in the pipelined sub-ADC.