Patents by Inventor Jon A. Masamitsu

Jon A. Masamitsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7389395
    Abstract: A heap may be marked and compacted while performing only two passes over the objects and object references in the heap. Specifically, objects and object references are traversed once during a marking phase and again during a compaction phase of split-reference, two-pass mark-compaction. Object references are updated in two steps. First, during marking, each object reference may be updated to include the relative offset within its block of the referenced object and-during compaction that offset may be added to the block's destination address resulting in a reference that points to the actual post-compaction location for the referenced object. Objects of a particular block may be rearranged, or permuted, with respect to each other within the block. However, the order between groups of objects in different blocks may be preserved across compaction.
    Type: Grant
    Filed: June 26, 2005
    Date of Patent: June 17, 2008
    Assignee: Sun Microsystems, Inc.
    Inventors: Alexander T. Garthwaite, David P. Stoutamire, Peter B. Kessler, Y Srinivas Ramakrisha, David L. Detlefs, Antonios Printezis, Jon A. Masamitsu, John W. Coomes
  • Patent number: 6195676
    Abstract: An integrated software architecture for a highly parallel multiprocessor system having multiple tightly-coupled processors that share a common memory efficiently controls the interface with and execution of programs on such a multiprocessor system. The software architecture combines a symmetrically integrated multithreaded operating system and an integrated parallel user environment. The operating system distributively implements an anarchy-based scheduling model for the scheduling of processes and resources by allowing each processor to access a single image of the operating system stored in the common memory that operates on a common set of operating system shared resources. The user environment provides a common visual representation for a plurality of program development tools that provide compilation, execution and debugging capabilities for multithreaded user programs and assumes parallelism as the standard mode of operation.
    Type: Grant
    Filed: January 11, 1993
    Date of Patent: February 27, 2001
    Assignee: Silicon Graphics, Inc.
    Inventors: George A. Spix, Diane M. Wengelski, Stuart W. Hawkinson, Mark D. Johnson, Jeremiah D. Burke, Keith J. Thompson, Gregory G. Gaertner, Giacomo G. Brussino, Richard E. Hessel, David M. Barkai, Steve S. Chen, Steven G. Oslon, Robert E. Strout, II, Jon A. Masamitsu, David M. Cox, Linda J. O'Gara, Kelly T. O'Hair, David A. Seberger, James C. Rasbold, Timothy J. Cramer, Don A. Van Dyke, Ashok Chandramouli
  • Patent number: 6042614
    Abstract: A system and method for providing a distributed debugger system for a distributed target computer application are disclosed wherein the programmer/developer of the application can be at one host machine and wherein the application being developed makes use of objects and object implementations which may be located on a different host machine which is unknown to the programmer/developer. The system and method provides solutions to problems which are encountered in trying to debug a new application which is associated with the use of objects in a widely distributed, object oriented, client-server system. In a distributed object environment, requests and replies are made through an Object Request Broker (ORB) that is aware of the locations and status of objects. One architecture which is suitable for implementing such an ORB is provided by the Common Object Request Broker Architecture (CORBA) specification.
    Type: Grant
    Filed: January 9, 1998
    Date of Patent: March 28, 2000
    Assignee: Sun Microsystems, Inc.
    Inventors: Andrew E. Davidson, Jon A. Masamitsu
  • Patent number: 5953530
    Abstract: The present invention is a system and method for a "debugger Run-Time-Checking for valid memory accesses for multi-threaded application programs" (hereinafter "RTC/MT") wherein a run-time process which includes multiple threads running either serially or concurrently, may be monitored by a debugger program and memory access errors detected and correctly attributed to the process thread encountering the error. The RTC/MT system of the present invention also provides an apparatus and method which monitors and reports memory leaks as required for multi-threaded target programs.
    Type: Grant
    Filed: November 25, 1997
    Date of Patent: September 14, 1999
    Assignee: Sun Microsystems, Inc.
    Inventors: Alok Rishi, Jon A. Masamitsu
  • Patent number: 5819093
    Abstract: A system and method for providing a distributed debugger system for a distributed target computer application are disclosed wherein the programmer/developer of the application can be at one host machine and wherein the application being developed makes use of objects and object implementations which may be located on a different host machine which is unknown to the programmer/developer. The system and method provides solutions to problems which are encountered in trying to debug a new application which is associated with the use of objects in a widely distributed, object oriented, client-server system. In a distributed object environment, requests and replies are made through an Object Request Broker (ORB) that is aware of the locations and status of objects. One architecture which is suitable for implementing such an ORB is provided by the Common Object Request Broker Architecture (CORBA) specification.
    Type: Grant
    Filed: March 3, 1995
    Date of Patent: October 6, 1998
    Assignee: Sun Microsystems, Inc.
    Inventors: Andrew E. Davidson, Jon A. Masamitsu
  • Patent number: 5339415
    Abstract: On a tightly coupled multiprocessor computer system, the multiple parallel regions of a multithreaded applications program can execute simultaneously as multiple threads on a plurality of processors. Furthermore, a plurality of multithreaded programs may run simultaneously. The current invention uses an efficient system to schedule and reschedule processors to run these multiple threads. Scheduling is integrated at two levels: at the first level, processors are assigned processes. At the next level, processes are assigned threads. Increased efficiency is achieved by this integration and also by the formation of processes with destructible context. It makes use of shared storage to indicate the process request level and the control state for each parallel region.
    Type: Grant
    Filed: November 9, 1992
    Date of Patent: August 16, 1994
    Assignee: Cray Research, Inc.
    Inventors: Robert E. Strout, II, George A. Spix, Jon A. Masamitsu, David M. Cox, Gregory G. Gaertner, Diane M. Wengelski, Keith J. Thompson
  • Patent number: 5179702
    Abstract: An integrated software architecture for a highly parallel multiprocessor system having multiple tightly-coupled processors that share a common memory efficiently controls the interface with and execution of programs on such a multiprocessor system. The software architecture combines a symmetrically integrated multithreaded operating system and an integrated parallel user environment. The operating system distributively implements an anarchy-based scheduling model for the scheduling of processes and resources by allowing each processor to access a single image of the operating system stored in the common memory that operates on a common set of operating system shared resources. The user environment provides a common visual representation for a plurality of program development tools that provide compilation, execution and debugging capabilities for multithreaded user programs and assumes parallelism as the standard mode of operation.
    Type: Grant
    Filed: June 11, 1990
    Date of Patent: January 12, 1993
    Assignee: Supercomputer Systems Limited Partnership
    Inventors: George A. Spix, Diane M. Wengelski, Stuart W. Hawkinson, Mark D. Johnson, Jeremiah D. Burke, Keith J. Thompson, Gregory G. Gaertner, Giacomo G. Brussino, Richard E. Hessel, David M. Barkai, Steve S. Chen, Steven G. Oslon, Robert E. Strout, II, Jon A. Masamitsu, David M. Cox, Linda J. O'Gara, Kelly T. O'Hair, David A. Seberger, James C. Rasbold, Timothy J. Cramer, Don A. Van Dyke, Ashok Chandramouli
  • Patent number: 5175856
    Abstract: A modular compilation system that utilizes a fully integrated hierarchical representation as a common intermediate representation to compile source code programs written in one or more procedural programming languages into an executable object code file. The structure of the integrated common intermediate representation supports machine-independent optimizations, as well as machine-dependent optimizations, and also supports source-level debugging of the executable object code file. The integrated hierarchical representation (IHR) is language independent and is shared by all of the components of the software development system, including the debugger.
    Type: Grant
    Filed: August 23, 1990
    Date of Patent: December 29, 1992
    Assignee: Supercomputer Systems Limited Partnership
    Inventors: Don A. Van Dyke, Timothy J. Cramer, James C. Rasbold, Kelly T. O'Hair, David M. Cox, David A. Seberger, Linda J. O'Gara, Jon A. Masamitsu, Robert E. Strout, II, Ashok Chandramouli