Patents by Inventor Jon C. Baker

Jon C. Baker has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7676769
    Abstract: Techniques for testing a semiconductor wafer are disclosed. One technique includes measuring a parameter for each of the semiconductor dies in a region of the wafer and determining an adaptive threshold for the region based on the measured parameters. The parameter measured for each die in the region is then compared to the adaptive threshold to determine a qualification status for each die. Accordingly, the semiconductor dies of the wafer are qualified based on an adaptive threshold that varies according to the wafer region under test. This allows for detection of dies whose parameters vary significantly from other dies in a region, providing for detection of potentially faulty dies whose parameter measurements otherwise meet a fixed threshold set for the entire wafer, such as a Single Threshold Test Limit (STL) expectation for the wafer.
    Type: Grant
    Filed: February 26, 2007
    Date of Patent: March 9, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Lai Chung Chan, Jon C. Baker
  • Publication number: 20080206903
    Abstract: Techniques for testing a semiconductor wafer are disclosed. One technique includes measuring a parameter for each of the semiconductor dies in a region of the wafer and determining an adaptive threshold for the region based on the measured parameters. The parameter measured for each die in the region is then compared to the adaptive threshold to determine a qualification status for each die. Accordingly, the semiconductor dies of the wafer are qualified based on an adaptive threshold that varies according to the wafer region under test. This allows for detection of dies whose parameters vary significantly from other dies in a region, providing for detection of potentially faulty dies whose parameter measurements otherwise meet a fixed threshold set for the entire wafer, such as a Single Threshold Test Limit (STL) expectation for the wafer.
    Type: Application
    Filed: February 26, 2007
    Publication date: August 28, 2008
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Lai Chung Chan, Jon C. Baker