Abstract: A data synchronizer (60) receives a data ready signal (40) at a selector (82). The selector (82) selects either the data ready signal (40) or a delayed version of the data ready signal (40) in response to a speed select signal (88) determined according to a clock speed of a receive core clock (52). The selector (82) provides a select signal (92) to a first latch unit (94) and a second latch unit (96). The first latch unit (94) generates a latched select signal (A) that is provided as a receive data valid signal (48) by a signal generator (108) in response to a slow clock rate for the receive core clock (52). The second latch unit (96) generates a delayed select signal (B) that is used by the signal generator (108) to remove an extra width inserted into the latched select signal (A) prior to providing the receive data valid signal (48) in response to a fast clock rate for the receive core clock (52).

Abstract: A system for binary multiplication based upon the modified Booth algorithm incorporating a Booth multiplex decoder, partial modified Booth arrays and partial product reduction adders. The system is comprised of Booth multiplexer cells, Booth multiplexer and adder cells, sign extension cells, and full adder cells interconnected such that the total adder delay through the system is n/4+1 adder delays where n is the number of bits in the multiplier.